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年間契約型資訊服務

商品編碼

1413686

先進封裝專利監測服務

Advanced Packaging Patent Monitoring Service

出版日期: 4 Issues/Year | 出版商:

KnowMade | 英文

價格

簡介目錄

該服務提供半導體先進封裝領域專利活動的最新數據（新專利申請數量、獲得的新專利數量、專利到期/放棄數量、專利轉讓數量以及專利訴訟的最新趨勢/反對）。等）。

服務主要特點

該報告提供最新的 Excel 資料庫（按季度）：

新專利申請數量
取得新專利數量
專利到期/放棄的數量
智慧財產權 (IP) 轉讓（重新分配、授權）和合作（聯合申請）數量
專利訴訟和異議
依封裝技術分類的專利：扇出封裝（晶圓級、面板級）、2.5D 和 3D 封裝（中介層、橋接器、混合鍵結、3D 堆疊記憶體）

每個季度，您都會收到以下 PDF 報告：

關鍵數據（季度）
透過圖表和評論介紹專利狀態的趨勢
各大知識產權公司及技術特寫

每年 100 小時與 IP 分析師接觸：

與智慧財產權分析師就季度分析結果、市場趨勢、分析內容、具體專利技術以及公司在先進封裝領域的智慧財產權組合進行問答和討論。

2.5D/3D 堆疊和扇出 WLP 是滿足半導體封裝市場需求的有前途的解決方案。監控主要半導體封裝公司的專利活動和智慧財產權策略至關重要。

在半導體產業，對單一包裝中更多運算能力和記憶體的需求不斷增長，以縮小外形尺寸並提高產品效能。然而，隨著節點達到其發展極限，摩爾定律變得越來越難以實現。因此，晶片小型化的進程正在放緩。2.5D和3D堆疊以及扇出晶圓級封裝等先進封裝技術已成為滿足半導體產業需求的重要解決方案。這些新方法能夠將多個晶片整合到單一封裝中，並有可能結合成熟和先進的節點，取代主導的倒裝晶片 (FC) 和引線鍵合 (WB) 互補技術。這些先進封裝技術的路線圖具有挑戰性，包括高密度扇出(HD FO) 重新分佈層(RDL)、高密度輸入/輸出互連(I/O) 以及矽中介層、嵌入式橋接器和混合鍵合對先進互連技術（例如小晶片方法）的需求正在加劇供應鏈競爭。2.5/3D 封裝市場具有最高的成長潛力，由於小晶片 3D 整合混合鍵合的普及，3D SoC 技術成長最快。在扇出 WLP 產業中，超高密度扇出 (UHD FO) 正在經歷最高的成長，因為與矽中介層相比，它已成為一種經濟高效的解決方案。半導體封裝主要由ASE/SPIL、Amkor 和 JCET等 OSAT 完成，它們繼續在該領域發揮重要作用。然而，TSMC、Samsung和Intel正在開發創新的 2.5D/3D 封裝解決方案，例如矽中介層、嵌入式橋和混合結。透過提供先進的後端解決方案並利用前端功能，這些公司有望影響該領域未來的技術和智慧財產權 (IP) 發展。

在此背景下，監控主要公司的專利活動和智慧財產權（IP）策略至關重要。這些知識可以幫助您了解競爭對手的研發路線圖和策略、評估風險並發現商機。我們的服務支援 TSMC、Intel、Samsung、Amkor、ASE、SPIL、JCET、Deca、Nepes、Powertech (PTI)、SJSemi、Tongfu (TFME)、Huatian、Infineon、Micron、SK Hynix、YMTC、GlobalFoundries、Xperi/Adeia 能夠定期了解各大公司的智慧財產權活動，例如

我們的服務利用每季更新一次的 Excel 資料庫，讓您能夠從季度分析報告以及與分析師的直接互動中受益。

專利監測服務優勢

您可以監控競爭對手的知識產權活動和未來意圖。

我們的服務使您能夠了解競爭對手目前的專利活動、智慧財產權動態、專利轉移（包括收購和授權）、專利訴訟、技術開發和研發策略。此外，可以在早期發現進入該業務領域的新進入者。

我們了解最新的技術趨勢並保持領先地位。

追蹤最近的專利申請趨勢可以讓您追蹤您所在領域的最新創新。獲取已提交發明的詳細資訊並追蹤技術發展。受新技術解決方案的啟發，研究和開發活動可能會得到改善。

您可以阻止註冊對您的業務有害的智慧財產權。

在授予專有權之前獲取有關已提交專利申請的信息，並迅速採取行動，防止可能對您的業務產生負面影響的知識產權註冊。

快速回應違規行為並降低法律風險。

監控新頒發的專利，以確保您的產品和工藝不受專利保護，並且您可以安全地製造它們，而不會侵犯他人擁有的有效智慧財產權。您可以定期評估您的銷售和使用的商業自由度。

利用免費技術降低研發專案的風險。

透過追蹤過期和廢棄的專利，您可以識別公共領域中可以安全用於您的開發的發明。

了解競爭對手目前的知識產權趨勢和策略。

每個季度，我們都會提供近三個月知識產權動態特寫，重點關注主要知識產權企業和主要專利技術。突出顯示了關鍵專利申請人及其發明、被阻止的專利、有前途的專利以及新到期或放棄的關鍵專利。

接觸知識產權分析師。

您將有機會透過電話或電子郵件與分析師直接互動，並透過問答和公開討論（每年 100 小時）獲取有關特定專利技術或公司智慧財產權組合的具體資訊。

目錄（樣本）

簡介/研究法

主要趨勢

近10年專利公開數量變化
扇出 (FO) 封裝
矽中介層
內建互連橋
混合連接
3D堆疊內存

市場概況（季度）

本季的主要事實
本季新發布/授予的同族專利
本季度過期或被放棄的專利
重大智慧財產權合作（聯合申請專利）
主要智慧財產權轉讓（專利權屬變更）
在美國發起和完成的智慧財產權訴訟數量
向 EP（歐洲專利局）提出的新異議數量

本季各公司的知識產權活動

專業鑄造廠

TSMC
GlobalFoundries

OSAT

Amkor
ASE
SPIL
JCET
Nepes
Powertech
Technology
Deca
Huatian
Technology
SJSemi
Tongfu
Microelectronics

IDM

Samsung
Infineon
Intel
Micron
SK
Hynix
YMTC

NPE

Xperi

附錄

簡介目錄

Get up-to-date data on Advanced Semiconductor Packaging patent activity: New patent applications, patents newly granted, expired or abandoned patents, latest patent transfers, patent litigations and oppositions.

Key Features of the service

Every quarter an up-to-date Excel database including:

New patents applications
Patent applications newly granted
Expired or abandoned patents
Transfer of IP rights (re-assignment, licensing) and IP collaborations (co-fillings)
Patent litigations and oppositions.
Patents categorized by packaging technologies: Fan-Out packaging (wafer level, panel level), 2.5D & 3D packaging (interposer, bridge, hybrid bonding, 3D-stacked memory)

Every quarter a PDF report including:

Key fact & figures of the quarter
Graphs & comments covering the patent landscape evolutions
A close look at the key IP players and technologies

Access to an IP analyst for 100 hours per year:

Q&A sessions and discussions with our IP analysts regarding quarterly report results, trends, analyses, specific patented technologies, or companies' IP portfolios in the field of Advanced Packaging.

2.5D/3D stacking and fan-out WLP are promising solutions to meet the needs of the semiconductor packaging market. It is crucial to monitor patent activity and IP strategies of key semiconductor packaging players

In the semiconductor industry, there is a growing demand for integrating more compute and memory within a single package in order to achieve smaller form factors and improve product performance. However, Moore's Law becomes increasingly difficult to achieve as node advancement reaches its limits. As a result, the process of chip miniaturization has been slowing down. Advanced packaging techniques, such as 2.5D & 3D stacking, and fan-out wafer level packaging, have emerged as crucial solutions to meet the needs of the semiconductor industry. These new approaches allow for the integration of multiple dies into a single package, with the possibility of combining mature and advanced nodes, and they have supplemented the dominant flip-chip (FC) and wire-bond (WB) technologies. The roadmap for these advanced packaging technologies is challenging and the supply chain is becoming increasingly competitive, with the demand for high-density fan-out (HD FO) redistribution layers (RDLs), high-density input/output interconnections (I/O), and advanced interconnect technologies such as silicon interposer, embedded bridge, hybrid bonding, and chiplets approach. The market for 2.5/3D packaging shows the most potential for growth, with 3D SoC technology growing the most driven by the increasing popularity of hybrid bonding for chiplets 3D integration. In the fan-out WLP industry, the segment experiencing the highest growth is the ultra-high density fan-out (UHD FO), which has emerged as a more cost-effective solution compared to silicon interposers. Semiconductor packaging was primarily performed by OSATs such as ASE/SPIL, Amkor, JCET, etc. and they continue to play an important role in this field. However, it is TSMC, Samsung and Intel that have been developing innovative 2.5D/3D packaging solutions such as silicon interposer, embedded bridge, and hybrid bonding. By offering advanced back-end solutions and using their front-end capabilities, these companies poised to influence future technology and intellectual property (IP) developments in this area.

In this context, it is crucial to monitor patent activity and intellectual property (IP) strategies of key players. Such knowledge can assist in understanding your competitors' R&D roadmap and strategies, evaluate the risks, and detect business opportunities. The Advanced Packaging Patent Monitor gives periodic insights on the IP activity of a selection of key companies: TSMC, Intel, Samsung, Amkor, ASE, SPIL, JCET, Deca, Nepes, Powertech (PTI), SJSemi, Tongfu (TFME), Huatian, Infineon, Micron, SK Hynix, YMTC, GlobalFoundries, and Xperi/Adeia.

The Advanced Packaging patent monitoring service allows you to take advantage of a quarterly-updated Excel database and benefit from both quarterly analysis reports and direct interaction with our analysts.

Benefits of the patent monitoring service

Keep a watch on your competitors' IP activities and their future intentions.

With the help of the patent monitoring service, you will be aware of your competitors' current patenting activities, their IP dynamics, patent transfers including acquisitions and licenses, patent litigation, technology development and R&D strategies. You will also be able to early detect new entrants in your business area.

Keep track of the latest technology developments and be ahead of technology trends.

By keeping note of any recent patent filings, you can track the newest innovations in the field. You will get details on claimed inventions and you can follow technology developments. New technical solutions could inspire and improve your R&D activity.

Prevent registration of IP rights that may be harmful to your business.

You will obtain information on patent applications filed even before exclusive rights have been granted and you can react in time to prevent registration of IP rights that may be harmful to your business.

React in time to infringements and mitigate legal risks.

Monitoring newly-issued patents allows you to regularly assess your freedom-to-operate, ensuring your products or processes are not covered by patents, and thus that they can be manufactured, sold or used safely without infringing valid IP rights owned by others.

Take advantage of free technologies and decrease R&D project risks.

By tracking both expired patents and abandoned patents, you will be able to identify inventions entering the public domain that you can use safely for your development.

Understand the current IP trends and IP strategy of competitors.

On a quarterly basis, the report will provide the IP trends over the three last months, with a close look to key IP players and key patented technologies. Main patent applicants and their inventions, blocking patents, promising patents and key patents newly expired or abandoned will be highlighted.

Access to the IP analyst.

Take advantage of direct interaction with our analysts by phone call and/or email and get specific input for specific patented technologies and company IP portfolios through Q&A session and open discussion (100h per year).