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市場調查報告書

電漿蝕刻:市場分析及策略性議題

Plasma Etching: Market Analysis and Strategic Issues

出版商 Information Network 商品編碼 4964
出版日期 內容資訊 英文 140 PAGES
商品交期: 2-3個工作天內
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電漿蝕刻:市場分析及策略性議題 Plasma Etching: Market Analysis and Strategic Issues
出版日期: 2021年05月01日內容資訊: 英文 140 PAGES
簡介

在VLSI電路系統製造上,一般認為取代了溼蝕刻的電漿蝕刻,已成為一門成熟的技術,但這門技術還是有它的動態,在新世代設備出現的同時也會出現新的課題。從前被批次系統支配的市場,目前正轉變為單晶圓式。

在尖端科技領域調查公司中具有世界級高度評價的美國調查公司The Information Network,將報告書” Plasma Etching: Market Analysis and Strategic Issues”即時(訂購當時更新內容)呈現給您。本報告所提供的市場預測分為批次及單晶圓反應器設計兩種。

本報告書內容概述如下。

1. 摘要整理

  • 技術上議題要點
  • 用戶相關議題要點
  • 供應商相關議題要點
  • 市場預測要點

2. 技術上議題及趨勢

  • 流程議題
  • 電漿光阻剝離
  • 安全相關議題

3. 市場預測

  • 技術趨勢對設備市場的影響
  • 市場預測的前提
  • 市場預測

4. 策略性議題:用戶

  • 用戶客制化的評估
  • 供應商的基準
  • 成本分析
  • 用戶與業者間的互補關係

5. 策略性議題:提供者

  • 競爭
  • 對客戶的回應
  • 對一級無塵室機器的回應
目錄

Etching equipment (or etcher) has high technology barriers due to the complexity and strict requirement of uniformity in the etching process, and etch is a key process in making critical dimensions within a chip. This area is primarily dominated by LAM Research, Tokyo Electron, and Applied Materials. These global leaders offer full etch equipment portfolio ranging from silicon etch (trench, gate, TSV), dielectric etch (Via, Contact, Side wall) and metal etch.

The etching process shapes thin films into certain patterns desired by wafer fabs by using chemicals, reaction gases or ion chemical reaction. In non-EUV, multi-patterning increases lithography and etch/cleaning steps. 14nm requires double-patterning, with KrF 193nm immersion DUV lithography tool, and 7nm requires quadruple-patterning. We see a rising number of etch steps as the process node moves to more advanced nodes, which could drive up etch demand. However, the use of EUV lithography tool in 7nm+ and 5nm could reduce the need for multi-patterning and thus reduce etching steps.

Advanced pulsing technology provides the extremely high materials selectivity, depth control and profile control needed by customers to create densely packed, high-aspect-ratio structures in 3D NAND, DRAM and logic, including FinFETs and emerging gate-all-around architectures.

This report addresses the strategic issues impacting both the user and supplier of plasma etching equipment to the semiconductor industry. Markets for dry etching and stripping are analyzed and projected, and market share presented by each sector.

Table of Contents

Chapter 1. Introduction

  • 1.1. The Need For This Report

Chapter 2. Executive Summary

  • 2.1. Summary of Technical Issues
  • 2.2. Summary of User Issues
  • 2.3. Summary of Supplier Issues
  • 2.4. Summary of Market Forecasts

Chapter 3. Technical Issues and Trends

  • 3.1. Introduction
  • 3.2. Processing Issues
    • 3.2.1. Chlorine Versus Fluorine Processes
    • 3.2.2. Multilevel Structures
    • 3.2.3. New Materials
    • 3.2.4. GaAs Processing
  • 3.3. Plasma Stripping
    • 3.3.1. Photoresist Stripping
    • 3.3.2. Low-K Removal
  • 3.4. Safety Issues
    • 3.4.1. System Design Considerations
    • 3.4.2. Gas Handling
    • 3.4.3. Reactor Cleaning

Chapter 4. Market Forecast

  • 4.1. Influence of Technology Trends on the Equipment Market
  • 4.2. Market Forecast Assumptions
  • 4.3. Market Analysis
    • 4.3.1. Plasma Etch and Plasma Strip Shares
    • 4.3.2. Market Forecasts

Chapter 5. Strategic Issues: Users

  • 5.1. Evaluating User Needs
    • 5.1.1. Device Architecture
    • 5.1.2. Wafer Starts and Throughput Requirements
    • 5.1.3. Wafer Size
  • 5.2. Benchmarking a Vendor
    • 5.2.1. Pricing
    • 5.2.2. Vendor Commitment and Attitudes
    • 5.2.3. Vendor Capabilities
    • 5.2.4. System Capabilities
  • 5.3. Cost Analysis
    • 5.3.1. Equipment Price
    • 5.3.2. Installation Costs
    • 5.3.3. Maintenance Costs
    • 5.3.4. Sustaining Costs
    • 5.3.5. Hidden Costs
  • 5.4. User - Supplier Synergy
    • 5.4.1. Feedback During Equipment Evaluation
    • 5.4.2. Feedback During Device Production

Chapter 6. Strategic Issues: Suppliers

  • 6.1. Competition
  • 6.2. Customer Interaction
    • 6.2.1. Customer Support
    • 6.2.2. Cleanroom Needs in the Applications Lab
  • 6.3. Equipment Compatibility in Class 1 Cleanrooms
    • 6.3.1. Footprint Versus Serviceability
    • 6.3.2. Particulate Generation
    • 6.3.3. Automation
    • 6.3.4. Etch Tools

LIST OF FIGURES

  • 3.1. Various Enhanced Designs (a) Helicon, (b) Multiple ECR, (c) Helical Resonator
  • 3.2. Schematic of Inductively Coupled Plasma Source
  • 3.3. Schematic of the HRe Source
  • 3.4. Schematic of the Dipole Magnet Source
  • 3.5. Schematic of Chemical Downstream Etch
  • 3.6. Silicon Trench Structure
  • 3.7. fin/STI Etch Requirements
  • 3.8. FinFET Gate Etch Requirements
  • 3.9. Dual Damascene Dielectric Etch Approaches
  • 4.1. Trends in Minimum Feature Size for Dynamic RAMS
  • 4.2. Market Shares for Dry Etch Equipment
  • 4.3. Market Shares for Strip Equipment
  • 4.4. Distribution of Etch Sales by Type
  • 4.5. Geographical Distribution of Equipment Revenues
  • 4.6. Etch System Demand by Geometry
  • 5.1. Typical First Year Single Wafer System Cost Analysis
  • 6.1. Relationship Between Device Yield and Particles
  • 6.2. Sources of Particles
  • 6.3. Relationship Between Die Yield and Chip Size

LIST OF TABLES

  • 3.1. Silicon Wafer Usage
  • 3.2. Plasma Source Comparison
  • 3.3. Typical Process Specifications
  • 4.1. Worldwide Dry Etch Market Shares
  • 4.2. Worldwide Dry Strip Market Shares
  • 4.3. Worldwide Market Forecast of Plasma Etching Systems
  • 4.4. Distribution of Etch Sales by Device by Vendor
  • 4.5. Number of Equipment Systems by Geometry
  • 5.1. Levels of Integration of Dynamic Rams
  • 5.2. Interconnect Levels of Logic Devices
  • 6.1. Etch Process Specifications