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市場調查報告書

FOWLP (扇出型晶圓級封裝)的專利環境

Fan-Out Wafer Level Packaging Patent Landscape

出版商 Knowmade 商品編碼 526010
出版日期 內容資訊 英文 200+ Pages PDF , Excel file (3,100+ patents)
商品交期: 最快1-2個工作天內
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FOWLP (扇出型晶圓級封裝)的專利環境 Fan-Out Wafer Level Packaging Patent Landscape
出版日期: 2016年11月30日 內容資訊: 英文 200+ Pages PDF , Excel file (3,100+ patents)
簡介

本報告提供全球FOWLP (扇出型晶圓級封裝)的專利趨勢調查,彙整專利公報·專利申請國·專利受讓人等趨勢的時間演變,主要專利受讓人的地位,相關訴訟,各技術區分趨勢,主要企業的IP簡介等資料。

簡介

市場趨勢

重要新聞

摘要整理

專利環境:概要

  • 專利申請的時間演變
  • 主要專利申請辦公室
  • 專利申請國的時間演變
  • 主要專利受讓人
  • 產業供應鏈
  • 技術的轉變
  • 主要專利受讓人的時間演變
  • 主要專利受讓人的加速
  • 專利受讓人的優先權觀察對象國家
  • 專利受讓人的專利申請國
  • 主要專利受讓人的專利法律地位
  • 已通過專利的殘餘有效期
  • 已通過專利·申請中專利的地區製圖
  • 已通過專利·申請中專利的觀察對象國家
  • 主要專利受讓人的申請
  • IP合作網路
  • 主要專利交易
  • 授權協定
  • 主要引用專利
  • 快到期的已通過專利等

主要專利受讓人的地位

  • IP特殊化的程度
  • 領先力量指標
  • IP龍頭
  • 封鎖性專利的潛力
  • IP的使用潛力
  • 最適合的IP的地位
  • 摘要:專利組合
  • 專利組合比較:主要IDM·晶圓代工廠·OSAT

專利相關訴訟

專利分析:各種類

  • 專利數量
  • 專利公報·主要專利受讓人的時間演變
  • 專利受讓人·技術區分的矩陣
  • 技術·流程階段&技術課題/架構的矩陣
  • 主要專利申請人·技術區分的矩陣

技術課題

主要企業的IP簡介

  • Infineon
  • NXP/Freescale
  • STATS ChipPAC
  • TSMC
  • ASE
  • Deca Technologies
  • Nepes
  • Nanium
  • SPIL
  • Amkor
  • Powertech Technology
  • Intel
  • STMicroelectronics
  • Samsung
  • NCAP
  • WiLAN
  • 3D PLUS
  • Apple

總論

目錄

FAN-OUT IP LANDSCAPE IS THE MOST DYNAMIC IN ADVANCED PACKAGING

With Apple and its A10 processor employing TSMC's InFO-PoP technology, the fan-out market has exploded. Apple's involvement will undoubtedly generate increased interest in the fan-out platform, and market revenue is forecast to reach around US$2.5B in 2021, with 80% growth between 2015 - 2017 (See Yole Développement's August 2016 report, Fan-out: Technology & Market Trends 2016). Moreover, following the high-volume adoption of InFO and the further development of fan-out wafer level packaging technologies, a wave of new players may enter the market. The supply chain is also expected to evolve, with a considerable amount of investment in Fan-Out packaging capabilities. In such a fast-growing Fan-Out market, it is essential to deeply understand the global patent landscape in order to anticipate changes, harvest business opportunities, mitigate risks, and make strategic decisions in order to strengthen one's market position and maximize return on one's IP portfolio. Knowmade has thoroughly investigated the Fan-Out packaging patent landscape (chip-first, chip-last, face-down, face-up, single-die, multi-chip module, package-on-package, system-in-package, etc.), and this report contains detailed patent analyses including countries of filing, patents' legal status, and patented technologies, as well as patent owners, their IP position, and IP strategies.

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More than 3,100 patents relating to over 1,200 inventions on Fan-Out packaging have been published worldwide through September 2016, coming from 100+ patent applicants. A first wave of patent applications occurred from 1999-2006, induced by Infineon. Patent applications have increased since then, with Freescale (NXP), STATS ChipPAC (JCET), SPIL, Amkor, and TSMC entering the Fan-Out IP arena. Today the number of enforceable patents is increasing worldwide, with several companies already standing out by virtue of their strong IP position. All of major players involved has filed patents on Fan-Out packaging, except for Nanium, which does not file any patents at all but instead has adopted a different IP strategy that we discuss in this report. Another special case is the presence of patent licensing companies like Polaris Innovations (WiLAN), which in 2015 acquired key patents from Infineon/Qimonda. The visibility of such companies in the patent landscape is a tangible sign of the market explodes. In the next few years Polaris Innovations could assert its patents to make money, and in this report we present its most critical patents. We have also noted Samsung's conspicuous IP presence in the FOWLP patent landscape, despite the company's unclear market position. R&D labs are also present (i.e. Fraunhofer, A*STAR, CEA), but to a lesser extent. Most new entrants in the FOWLP patent landscape are Chinese players (HuaTian Technology, NCAP, SMIC), and more recently we have observed Apple's appearance. Apple, which this year chose TSMC's InFO-PoP technology for its A10 APE, has recently filed some patents on Fan-Out wafer level packaging (chip-last, chip-first, PoP, and SiP), reflecting a genuine interest in the FOWLP platform.


KNOW THE KEY PLAYERS' IP POSITION

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This report analyzes in detail the IP status and IP strategies of key players and provides an understanding of their patented technologies. This report also provides a ranking and analysis of the top patent holders' relative strength, derived from their portfolio size, patent citation networks, countries of patent filing, and patents' current legal status. Furthermore, we reveal the IP strength of the key IP players involved in FOWLP technologies, and we depict their competitive IP position. JCET/STATS ChipPAC and TSMC lead the FOWLP patent landscape. From a quantitative point of view, TSMC is the most prolific patent applicant of the last few years, but according to our analyses, JCET/STATS ChipPAC has by far the strongest IP position. The company has formidable "IP blocking potential" that empowers it to deter other players to patent inventions that are similar to its own IP portfolio. TSMC is the most serious IP challenger, and it may reshape the patent landscape in the near future upon the approval of its numerous pending patent applications. Both companies feature a large enforceable patent portfolio and a long remaining lifetime of their patents.


PATENTED TECHNOLOGY AND IP STRATEGY

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The 1,200+ inventions selected for this study are categorized by technology solution (chip-first/face-down, chip-first/face-up, chip-last), process steps (die placement, molding, planarization, RDL), architecture (multi-chip module, PoP, SiP, face-to-face package, etc.) and technical challenges (warpage, die shift). In this report we also reveal the IP strategy and technical choices of the main patent assignees. A special focus is placed on technical solutions found in patents for solving warpage and die shift issues. This report also provides an IP profile for 18 key players: Infineon, NXP/Freescale, STATS ChipPAC, TSMC, ASE, Deca Technologies, Nepes, Nanium, SPIL, Amkor, Powertech Technology, Intel, STMicroelectronics, Samsung, NCAP, WiLAN, 3D PLUS, and Apple. Each company's IP profile includes the time evolution of their patent applications, a world map of granted patents and pending patent applications, and key features and strength of their patent portfolio.


USEFUL PATENT DATABASE (3,100+ patents)

This report also includes an Excel database containing the 3,100+ patents analyzed in our study. This useful patent database allows for multi-criteria searches and includes patent publication number, hyperlinks to the original documents, priority date, title, abstract, patent assignees, technological segments, and legal status for each patent family member.

COMPANIES MENTIONED IN THE REPORT

3D Plus, A*STAR, ACE Technology, ADL Engineering, Altera, Amkor, Apple, ASE, Avago Technologies, Bridge Semiconductor, Bridgelux, Broadcom, Camtek, CEA, Cheng Ming, ChipMOS, Cirrus Logic, Conexant Systems, Cypress Semiconductor, Dainippon Screen Manufacturing, Deca Technologies, EPIC Technologies, EV Group, Flipchip International, Fraunhofer, Fujitsu, GE Embedded Electronics, General Electric, Gerad Technologies, GlobalFoundries, Hana Micron, Hitachi Chemical, HuaTian Technology, Infineon, Intel, ITRI (Industrial Technology Research Institute), JCAP, JCET/STATS ChipPAC, J-Devices, Jiangsu University of Science & Technology, LSI Logic, Macrotech Technology, Maxim Integrated Products, MediaTek, Medtronic, Micron Technology, Murata Electronics, NCAP, Nepes, Niko Semiconductor, Nippon Electric Glass, Nitto Denko, North Star Innovations (WiLAN), NXP/Freescale, Nytell Software, Oerlikon, PacTech Packaging Technologies, Philips, Polaris Innovations (WiLAN), Powertech Technology, Princo Middle East FZE, Qimonda, Qualcomm, Renesas Electronics, Samsung Electronics, Samsung Electro Mechanics, Semiconductor Components Industries, Seoul National University (SNU), Sharp, Shinko Electric Industries, SK Hynix, SMIC, Sony, Sound Technology, SPIL, STMicroelectronics, Technische Universitat Berlin, Tera Probe, Tessera, Texas Instruments, Toray Advanced Mat Korea, Toshiba, TSMC, Ultratech, Unimicron Technology, United Microelectronics, United Test & Assembly Center, X-Celeprint, Xenogenic Development (Intellectual Ventures), Xilinx, Xintec, Zhongxin Changdian Semiconductor ...

Table of Contents

INTRODUCTION

  • Definitions
  • Scope of the report
  • Key features of the report
  • Objectives of the reports
  • Methodology

MARKET TRENDS

NOTEWORTHY NEWS

EXECUTIVE SUMMARY

PATENT LANDSCAPE OVERVIEW

  • Time evolution of patent applications
  • Major offices of patent applications
  • Time evolution of patent applications by country
  • Main patent assignees
  • Industry supply-chain
  • Technology history
  • Time evolution of main patent assignees
  • Acceleration of main patent assignees
  • Countries of priority patents for patent assignees
  • Countries of patent filings for patent assignees
  • Legal status of patents for main patent assignees
  • Remaining lifetime of granted patents
  • Geographic map of granted patents and pending patent applications
  • Countries of granted patents and pending patent Applications for main patent assignees
  • IP collaboration network
  • Main patent transactions
  • Licensing agreements
  • IP competitors dependency by patent citations
  • Most cited patents
  • Granted patents near expiration date

IP POSITION OF MAIN PATENT ASSIGNEES

  • IP specialization degree
  • Prior art strength index
  • IP leadership
  • IP blocking potential
  • IP enforcement potential
  • The best IP positions
  • Summary of patent portfolios
  • Comparison of patent portfolios of the main IDMs, Foundries and OSATs

PATENT LITIGATIONS

PATENT SEGMENTATION

For each segment: number of patents, time evolution of patent publications and main patent assignees, Matrix of patent assignees vs. technical segments, Matrix of technology vs. process steps & technical challenges/architecture, Matrix of main patent applicants vs. technical segments

TECHNICAL CHALLENGES

  • Solutions found in patents to solve warpage and die shift issues

IP PROFILE OF KEY PLAYERS

Infineon, NXP/Freescale, STATS ChipPAC, TSMC, ASE, Deca Technologies, Nepes, Nanium, SPIL, Amkor, Powertech Technology, Intel, STMicroelectronics, Samsung, NCAP, WiLAN, 3D PLUS, Apple.

Each IP profile includes: time evolution of patent applications, world map of granted patents and pending patent applications, key features and strength of patent portfolio.

CONCLUSION

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