Through-Silicon Via (TSV) is a vertical electrical connection that passes completely through a silicon wafer or chip to create 3D ICs or packages. The drivers for market adoption of 3D ICs are increased performance, reduced form factor and cost reduction. TSV provides the high-bandwidth interconnection between stacked chips. The different TSV processes, which are more complex than initially anticipated, are analyzed.
This report analyzes the market for TSV ICs by units and wafers, and for equipment and materials used in their manufacture.
Table of Contents
Chapter 1. Introduction
Chapter 2. Insight Into Critical Issues
- 2.1. Driving Forces In 3-D TSV
- 2.2. Benefits of 3-D ICs With TSVs
- 2.3. Requirements For A Cost Effective 3-D Die Stacking Technology
- 2.4. TSV Technology Challenges
- 2.5. TSV Supply Chain Challenge
- 2.6. Limitations of 3-D Packaging Technology
- 2.6.1. Thermal Management
- 2.6.2. Cost
- 2.6.3. Design Complexity
- 2.6.4. Time to Delivery
Chapter 3. Cost Structure
- 3.1. Cost Structure of 3-D chip Stacks
- 3.2. Cost of Ownership
Chapter 4. Critical Processing Technologies
- 4.1. Introduction
- 4.2. Cu Plating
- 4.3. Lithography
- 4.3.1. Optical Lithography
- 4.3.2. Imprint Lithography
- 4.3.3. Resist Coat
- 4.4. Plasma Etch Technology
- 4.5. Stripping/Cleaning
- 4.6. Thin Wafer Bonding
- 4.7. Wafer Thinning/CMP
- 4.8. Stacking
- 4.9. Metrology/Inspection
Chapter 5. Evaluation Of Critical Development Segments
- 5.1. Introduction
- 5.2. Via-first
- 5.2.1. Equipment Requirements
- 5.2.2. Material Requirements
- 5.3. Via-Middle
- 5.3.1. Equipment Requirements
- 5.3.2. Material Requirements
- 5.4. Via-Last
- 5.4.1. Equipment Requirements
- 5.4.2. Material Requirements
- 5.5. Interposers
Chapter 6. Profiles Of Participants
- 6.1. Chip Manufacturers/Packaging Houses/Services
- 6.2. Equipment Suppliers
- 6.3. Material Suppliers
- 6.4. R&D
Chapter 7. Market Analysis
- 7.1. TSV Device Roadmap
- 7.2. TSV Device Forecast
- 7.3. Equipment Forecast
- 7.4. Material Forecast