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3D NAND的堆疊方法

How 3D NAND Stacks Up

出版商 Forward Insights 商品編碼 294041
出版日期 內容資訊 英文 121 Pages
商品交期: 最快1-2個工作天內
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3D NAND的堆疊方法 How 3D NAND Stacks Up
出版日期: 2014年01月01日 內容資訊: 英文 121 Pages


本報告提供3D NAND的替代技術比較、課題、優點與缺點相關的獨自見解、弄清3D NAND的主要製造商狀況等,為您概述為以下內容。






  • NAND快閃記憶體技術的演進
  • 浮動閘極記憶體單元微縮的課題
  • NAND的替代技術:電荷設陷型記憶體單元

3D NAND的替代

  • 傳統的方法
  • Samsung是以單晶沉積堆疊
  • 非傳統的方法
  • 水平通道:水平閘極
  • 垂直閘極:Macronix TFT - Samsung VG-NAND
  • 垂直通道:穿孔結構
  • 東芝BiCS
  • Samsung TCAT
  • Hynix的垂直圓柱形浮閘
  • SK Hynix SMArT:Stacked Memory Array Transistor
  • 垂直通道:通道的環繞式結構
  • Samsung VSAT:Vertical Stacked Array Transistor


  • 單元的尺寸
  • 阻礙因素
  • 單元的效率
  • 每1單元功能的位元數
  • 收穫率
  • 性能
  • 耐用性
  • 記憶力
  • 消耗功率
  • 擴充性
  • 摘要


  • 3D NAND狀況
    • Intel/Micron
    • Macronix
    • Samsung
    • SanDisk/Toshiba
    • SK Hynix
  • 3D NAND發展藍圖
  • 3D NAND的成本趨勢




關於Forward Insights



Product Code: FI-NFL-3DM-0114

The NAND flash industry is at a technology inflection point. Planar floating gate NAND flash memory is facing fundamental scaling challenges with the upcoming 16nm node the last generation of planar technology. What's next?

Samsung's August 2013 announcement of the production of a 24-layer vertical string V-NAND shows the way forward. Vertical NAND or 3D NAND promises to continue increases in storage capacities and lower cost per bit necessary to enable emerging applications such as solid state drives and cold flash.

In the 2D planar era, the basic underlying floating gate technology (with a few exceptions) was essentially the same amongst all the NAND flash manufacturers. However in the 3D era, all NAND flash memory manufacturers are developing different 3D architectures. How 3D NAND Stacks Up compares the 3D NAND alternatives and provides an independent view of the challenges, advantages and disadvantages of the various implementations and illuminates the 3D NAND status of the major industry players.

Table of Contents


List of Figures

List of Tables

Executive Summary


NAND Flash Memory

  • NAND Flash Memory Technology Evolution
  • Floating Gate Memory Cell Scaling Challenges
    • Program Voltages and WL-WL Dielectric Breakdown
    • Number of Floating Gate Electrons, Charge Cross-talk, and Random Telegraph Noise
    • IPD Scaling of Electrical Thickness and Program Saturation: Can a Planar Cell be a Solution?
  • NAND alternative: Charge Trapping Memory Cell

3D NAND Alternatives

  • Conventional Approach
  • Samsung Stacking by Single Crystal Deposition
    • Concept
    • Advantages and Disadvantages
    • Challenges
  • Nonconventional approach
  • Horizontal channel - horizontal gate
    • Concept
    • Advantages/Disadvantages
    • Challenges
  • Vertical gate - Macronix TFT - Samsung VG-NAND
    • Concept
    • Advantages/Disadvantages
    • Challenges
  • Vertical Channel - Punch Structure
  • Toshiba BiCS
    • Concept - 1st Generation
    • Advantages and Disadvantages
    • Concept - 2nd Generation à p-BiCS structure
    • Challenges
  • Samsung TCAT
    • Concept
    • Advantages
    • Disadvantages
    • Challenges
  • Hynix Vertical Cylindrical Floating-gate
    • Concept
    • Advantages
    • Disadvantages
    • Challenges
  • SK Hynix SMArT - Stacked Memory Array Transistor
    • Concept
    • Advantages
    • Disadvantages
    • Challenges
  • Vertical Channel - Channel Wrap-around Structure
  • Samsung VSAT - Vertical Stacked Array Transistor
    • Concept
    • Advantages
    • Disadvantages
    • Challenges

Comparison of 3D Memory Concepts

  • Cell Size
  • Disturbs
  • Cell Efficiency
  • Number of Bits per cell Capability
  • Yield
  • Performance
  • Endurance
  • Retention
  • Power Consumption
  • Stackability
  • Summary


  • 3D NAND Status
    • Intel/Micron
    • Macronix
    • Samsung
    • SanDisk/Toshiba
    • SK Hynix
  • 3D NAND Roadmap
  • 3D NAND Cost Trend


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