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市場調查報告書

中國SMIC·JCET間的晶圓凸塊(Wafer Bumping)相關企業合作及對全球半導體產業的影響

SMIC-JCET Strategic Cooperation on Wafer Bumping and Its Effects on the Global Semiconductor Industry

出版商 Market Intelligence & Consulting Institute (MIC) 商品編碼 300907
出版日期 內容資訊 英文 13 Pages
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中國SMIC·JCET間的晶圓凸塊(Wafer Bumping)相關企業合作及對全球半導體產業的影響 SMIC-JCET Strategic Cooperation on Wafer Bumping and Its Effects on the Global Semiconductor Industry
出版日期: 2014年04月29日 內容資訊: 英文 13 Pages
簡介

受到中國政府以透過本國系企業的半導體產業為目標的聲明(2014年2月)之影響,中國大型晶圓、晶圓代工廠SMIC(Semiconductor Manufacturing International Corporation)和大型構裝服務供應商JCET(Jiangsu Changjiang Electronics Technology Co.),發表將合力建造12英吋形式的晶圓凸塊(Wafer Bumping)·檢驗設備。資本支出比例預定為SMIC方面佔51%、JCET方面佔49%。

本報告提供此次的SMIC·JCET兩家公司企業合作概要及要因調查,加上中國國內半導體產業的發展狀況及今後預測、對世界半導體產業的影響等考察,並將結果概述為以下內容。

第1章 背景情況

第2章 凸塊(Wafer Bumping):在高度IC製造技術上,改善晶圓產量低比率的關鍵

  • SMIC至今仍以0.15/0.18nm為主體,高度製造流程的佔有率仍停滯於低水準
  • TSMC在40/45nm晶圓的佔有率超過50%
  • 晶圓凸塊(Wafer Bumping)技術這個照亮高度構裝能力的指標
  • IC廠商與構裝·服務供應商為提升凸塊(Wafer Bumping)能力的措施

第3章 企業間合作的理由和要素

  • SMIC的目標:透過晶圓凸塊(Wafer Bumping)改善大量生產速度
  • 透過企業間合作,降低晶圓凸塊(Wafer Bumping)相關的風險

第4章 結論

  • 以中國政府提供的資金供給為目的的MIC和JCET合作體制
  • 企業間合作是否能成為改變高階IC製造業市場環境的要素

附錄

圖表一覽

目錄
Product Code: SCRPT14042901

In the wake of the declaration made by China's government to make efforts to build an indigenous semiconductor industry in February 2014, SMIC (Semiconductor Manufacturing International Corporation) - China's leading wafer foundry - and JCET (Jiangsu Changjiang Electronics Technology Co.) - the leading packaging service provider in China - announced that they will jointly build an 12" bumping and testing facility, in which SMIC and JCET holds 51% and 49% stake, respectively. This report points out the reasons behind the SMIC-JCET cooperation and provides in-depth analysis of China's rise and the consequences thereof for the global semiconductor industry.

Table of Contents

List of Topics

1. Background

2. Bumping a Key for Improved Wafer Yields of Advanced IC Manufacturing Technologies

  • 2.1. SMIC Still Centers on 0.15/0.18nm and Its Advanced Manufacturing Process Share Remains Slim
  • 2.2. TSMC's 40/45nm Wafer Share Topped Over 50%
  • 2.3. Wafer Bumping Technology as an Indicator to Prove Advanced Packaging Capabilities
  • 2.4. IC Manufacturers and Packaging Service Providers to Ramp Up Bumping Capacity

3. Reasons and Factors behind the Cooperation

  • 3.1. Wafer-bumping to Help SMIC Increase Mass Production Speed
  • 3.2. Cooperation to Reduce Risks Associated with Wafer Bumping

4. Conclusion

  • 4.1. SMIC-JCET Cooperation Take Aims at Chinese Government Funding
  • 4.2. The Cooperation Might Make a Stir on Market Landscape of High-end IC Manfuacturing
  • Appendix

List of Figures

  • Figue 1: SMIC Revenue Share by Process Technology, 1Q 2011 - 4Q 2013
  • Figue 2: TSMC Revenue Share by Process Technology, 1Q 2011 - 4Q 2013

List of Tables

  • Table 1: Chinese Indigenous IC Foundries and News
  • Table 2: Chinese Wafer Bumping Patent Applicants and Holders
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