覆晶/WLP的製造與市場分析

Flip Chip/WLP Manufacturing and Market Analysis

出版日期: 2024年03月01日 | 出版商:

Information Network | 英文 | 商品交期: 2-3個工作天內

價格

簡介目錄

本報告提供覆晶技術和WLP的技術市場相關調查，各類型的問題趨勢，市場預測與課題等相關彙整資訊。

Advanced wafer-level packaging technologies hold the key to meeting future technology needs, from mobile devices to automotive applications, to those required for enabling the IoT. Flip chip technology is slowly replacing wire bonding for many high-performance chips. Flip Chip (FC) is not a specific package (like SOIC), or even a package type (like BGA). Flip Chip describes the method of electrically connecting the die to the package carrier whereby the interconnection between the die and carrier is made through a conductive "bump" or copper pillar that is placed directly on the die surface. The bumped die is then "flipped over" and placed face down, with the bumps connecting to the carrier directly.

This technology can be applied on application processor, baseband, PMIC, memory devices, etc. products. For mobile communications, flip chip development is driven by increased device performance and package miniaturization trends, particularly for the CPU or so called applications processor that powers smart phones and media tablets.

To meet the needs of thinner mobile devices, Wafer Level Packages (WLPs) have been developed. They differ from flip-chip packages primarily in that the die is mounted directly on the PCB. The reduced form factor provided by mounting the die directly on the PCB has vaulted WLP to the leading position for smartphones and other products where space is at a premium.

This report analyzes the technology for flip chip technology and WLPs, presenting forecasts for packages by type and application.

Chapter 1 Introduction

Chapter 2 Executive Summary

Chapter 3 Flip Chip/WLP Issues and Trends

3.1. Introduction
3.2. Wafer Bumping
- 3.2.1. Solder Bumps
  - 3.2.1.1 Metallurgy
  - 3.2.1.2 Deposition Of UBM
  - 3.2.1.3 Sputter Etching
  - 3.2.1.4 Photolithography
  - 3.2.1.5 Solder Deposition
  - 3.2.1.6 Resist Strip
  - 3.2.1.7 UBM Wet Etch
  - 3.2.1.8 Reflow
  - 3.2.1.9 Flux Issues
- 3.2.2. Gold Bumps
  - 3.2.2.1 Bump Processing
  - 3.2.2.2 Bonding
  - 3.2.2.3 Coplanarity
  - 3.2.2.4 Conductivity
  - 3.2.2.5 Thermal Properties
  - 3.2.2.6 Size
  - 3.2.2.7 Reliability
  - 3.2.2.8 Cost Issues
- 3.2.3. Copper Pillar Bumps
- 3.2.4. Copper Stud Bumping
- 3.2.5. C4NP
3.3. Wafer Level Packaging
3.4. Pad Redistribution
3.5. Wafer Bumping Costs
- 3.5.1. Wafer Redistribution And Wafer Bumping Costs
- 3.5.2. WLCSP Hidden Costs
- 3.5.3. WLCSP Cost Per Good Die
- 3.5.4. Wafer-Level Underfill Costs
3.6. Panel Level Packaging

Chapter 4 Lithography Issues And Trends

4.1. Issues
- 4.1.1. Technical Performance
- 4.1.2. Capital Investment
- 4.1.3. Cost Of Consumables
- 4.1.4. Throughput
- 4.1.5. Ease Of Use
- 4.1.6. Flexibility
- 4.1.7. Equipment Support
- 4.1.8. Resolution
- 4.1.9. Solder Bumping Capabilities
- 4.1.10. Gold Bumping Capabilities
4.2. Exposure Systems
- 4.2.1. Introduction
  - 4.2.1.1 Reduction Steppers
  - 4.2.1.2 Full-Field Projection
  - 4.2.1.3 Mask Aligners
  - 4.2.1.4 1X Steppers
  - 4.2.1.5 2X Steppers
4.3. Competitive Technologies
- 4.3.1. Inkjet Printing
- 4.3.2. Stencil/Screen Printing
- 4.3.3. Electroless Metal Deposition

Chapter 5 UBM Etch Issues And Trends

5.1. Introduction
5.2. Technology Issues And Trends
- 5.2.1. Process Flow
- 5.2.2. Etch Process
- 5.2.3. Etch Chemistry
5.3 Batch Versus Single-Wafer Etching

Chapter 6 Metallization Issues and Trends

6.1. Introduction
6.2. Sputtering Metallization
- 6.2.1. Gold Bump
- 6.2.2. Solder Bumping
  - 6.2.2.1 T i / Cu and TiW / Cu
  - 6.2.2.2 Al / NiV / Cu
  - 6.2.2.3 T i / N i (V) and TiW / Ni ( V )
  - 6.2.2.4 Cr / Cr-Cu / Cu
- 6.2.3. Copper Bumping
6.3. Electrodeposition