|
市場調查報告書
多位元/單元NAND型快閃記憶體之讀取結構
Read Architectures for Multi-bit per cell NAND Flash Memories
|
多位元/單元NAND型快閃記憶體之讀取結構 是由出版商Forward Insights在2009年09月所出版的。
這份英文市場調查報告書包含36 Pages 價格從美金2999起跳。
Abstract
This report explores the theory, circuit elements, timings, and key design
features of the conventional interleaved architecture versus the all bitline
sensing architecture.
Table of Contents
- CONTENTS
- LIST OF FIGURES
- EXECUTIVE SUMMARY
- INTRODUCTION
- NAND FLASH READ ARCHITECTURES
- Conventional Read Architecture
- All Bitline Sensing (ABL) Architecture
- ABL Sensing vs. Conventional Read
- REFERENCES
- ABOUT THE AUTHOR
- ABOUT FORWARD INSIGHTS
- REPORT OFFERINGS
List of Figures
- Figure 1. NAND Architecture
- Figure 3. Conventional Read: Essential Elements of the Page Buffer
- Figure 4. Conventional Read Timing
- Figure 5. Conventional Read Latches
- Figure 6. Conventional Read: Latch characteristic for appropriate sizing
- Figure 7. ABL sensing: Essential Elements of the Page Buffer
- Figure 9. ABL sensing: the sense
- Figure 10 Evaluation Time
- Figure 11. Contributors to Parasitic Capacitance (Bitline cross-section)
- Figure 12 Three adjacent bitlines and the effect of capacitive coupling
between them
- Figure 13 Yupin Effect
- Figure 14. Cell working points
- Figure 17 Programming Time for 2-bit/cell NAND Flash Memory
- Figure 19 Energy Savings
- Figure 20 3-bit/cell ABL Programming
List of Tables
- Table 1. ABL vs. Conventional Read Architecture
|
