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市場調查報告書
主要NAND型快閃記憶體設計的智慧財產權
Key NAND Flash Memory Design Intellectual Property
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主要NAND型快閃記憶體設計的智慧財產權 是由出版商Forward Insights在2009年07月所出版的。
這份英文市場調查報告書包含152 Pages 價格從美金9999起跳。
主要NAND型快閃記憶體設計的智慧財產權
本報告書內容包括：NAND型快閃記憶體的感應架構、電源電壓的雜訊補償、可編程演算法等相關主要智慧財產權調查分析、多重NAND型快閃記憶體的課題等。內容綱要摘記如下：
- 調查方法
- 多重NAND型快閃記憶體的課題
- 主要NAND型快閃記憶體的智慧財產權
- 多重記憶體的感應架構
- 電源電壓的雜訊補償
- 粗微動程式
- 循頁編程
- 降低浮停閘間的雜訊耦合及對背景模式的依賴
- 改善感應及分頁負載量
- 負的閾値感應
- 程式干擾
- 溫度補償
- 高電壓開關
- 充電幫浦
- 符號化機制及錯誤訂正編碼
- 參考資料
- 著者介紹
- 圖表
專利所有權者
- Hynix
- Micron
- Samsung
- SanDisk
- STMicroelectronics
- 東芝
Abstract
Technical innovations, particularly in NAND flash memory design are key
enablers of multi-level cell NAND flash memories, especially 3-bit per cell
and 4-bit per cell technologies. This report identifies important intellectual
property related to sensing architectures, source voltage noise compensation,
programming algorithms, disturbs reduction, temperature compensation, high
voltage switch, coding schemes and error correction codes from Hynix, Micron,
Samsung, SanDisk, STMicroelectronics and Toshiba.
Table of Contents
- Contents
- List of Figures
- Methodology
- Issues Inherent in Multi-state NAND Flash Memory
- Key NAND Flash Intellectual Property
- Sensing Architecture for Multi-state Memories
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- Source Voltage Noise Compensation
- US Patent Application No.
- U.S. Patent No.
- Coarse and Fine Programming
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- Sequential page programming
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- Floating Gate-Floating Gate Noise Coupling Reduction and Background
Pattern Dependency
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent Application No.
- U.S. Patent Application No.
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- Sensing and Page Buffer Improvements
- U.S. Patent No.
- U.S. Patent No.
- Negative Threshold Sensing
- U.S. Patent No.
- U.S. Patent No.
- Program Disturb
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent Application No.
- U.S. Patent Application No.
- Temperature Compensation
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- High Voltage Switch
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- Charge Pumps
- U.S. Patent No.
- U.S. Patent No.
- U.S. Patent No.
- Coding Schemes and Error Correction Codes
- U.S. Patent No.
- U.S. Patent Application No.
- U.S. Patent Application No.
- U.S. Patent Application No.
- U.S. Patent No.
- U.S. Patent Application No.
- U.S. Patent No.
- U.S. Patent No. .156
- U.S. Patent Application No.
- References
- About the Author
- About Forward Insights
List of Figures
- Figure 1
- Figure 2
- Figure 3
- Figure 4
- Figure 5
- Figure 6
- Figure 7
- Figure 8
- Figure 9
- Figure 10
- Figure 11
- Figure 12
- Figure 13
- Figure 14
- Figure 15
- Figure 16
- Figure 17
- Figure 18
- Figure 19
- Figure 21
- Figure 23
- Figure 24
- Figure 25
- Figure 26
- Figure 27
- Figure 28
- Figure 29
- Figure 30
- Figure 31
- Figure 32
- Figure 33
- Figure 34
- Figure 35
- Figure 36
- Figure 37
- Figure 38
- Figure 39
- Figure 41
- Figure 42
- Figure 43
- Figure 44
- Figure 45
- Figure 46
- Figure 47
- Figure 48
- Figure 49
- Figure 50
- Figure 51
- Figure 52
- Figure 53
- Figure 54
- Figure 55
- Figure 56
- Figure 57
- Figure 58
- Figure 59
- Figure 60
- Figure 61
- Figure 62
- Figure 63
- Figure 64
- Figure 65
- Figure 66
- Figure 67
- Figure 68
- Figure 69
- Figure 70
- Figure 71
- Figure 72
- Figure 73
- Figure 74
- Figure 75
- Figure 76
- Figure 77
- Figure 78
- Figure 79
- Figure 80
- Figure 81
- Figure 82
- Figure 80
- Figure 81
- Figure 82
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