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市場調查報告書

Ericsson RBS6000數位基頻單位ASIC

Ericsson RBS6000 Digital Baseband Units, ASICs Report

出版商 EJL Wireless Research 商品編碼 337819
出版日期 內容資訊 英文 144 Pages
商品交期: 最快1-2個工作天內
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Ericsson RBS6000數位基頻單位ASIC Ericsson RBS6000 Digital Baseband Units, ASICs Report
出版日期: 2015年07月31日 內容資訊: 英文 144 Pages
簡介

本報告提供Ericsson的RBS6000基地台平台的數位基頻單位所採用的ASIC的相關調查、ERICSSON的無線系統結構、數位單位 (DU) 概要、DSP核心分析、各種ASIC的晶粒尺寸、封裝、照片、製圖等詳細內容相關彙整。

摘要整理

第1章 ERICSSON的無線系統結構

  • DU的面板與其ASIC
  • Ericsson無線系統結構
  • 軟體無線電
  • 多重標準RAN的複雜性
  • All RAN的Ericsson無線系統
  • DU ASIC表(圖表):概要

第2章 數位單位 (DU) 概要

  • DU系統層級架構的ASIC支援
  • DU面板層級架構
  • DUG子系統
  • DUW子系統
  • DUL&DUS子系統
  • 共同的營運和O&M的特徵
  • 面板/ASIC追蹤&調試概要

第3章 RBS數位單位 (DU) 的處理

  • DU分析:範圍/流程
  • DUL/DUS子系統的功能
  • 詳細的ASIC分析流程
  • 多核心的生態系統
  • 非定型的追蹤&調試功能
  • DU架構的摘要

第4章 DU ASIC概要

  • ASIC流程節點
  • ASIC構造來源分析
  • 矽區域與機能
  • DSP/多核心進化

第5章 多核心/DSP概要

  • 從PowerPCR轉變到ARM生態系統
  • DSP核心科技/分析
  • 內部DSP核心

第6章 GSM用DUG ASIC

  • GSM處理概要
  • 基本結構與架構
  • I/O分析
  • DUG ASIC-2:調查結果的摘要

第7章 W-CDMA用DUW ASIC

  • DUW ASIC概要
  • DUW ASIC #1:封裝分析
  • DUW ASIC #1:晶片分析
  • DUW ASIC #1:功能分析
  • DUW ASIC #2:封裝分析
  • DUW ASIC #2:晶片分析
  • DUW ASIC #2:特殊結構

第8章 DUL ASIC分析

  • DUL ASIC概要
  • DUL ASIC:封裝分析
  • DUL ASIC:晶片分析
  • DUL ASIC:CPU的功能
  • DSP的功能
  • 數位&類比I/O

第9章 DUS ASIC分析

  • DUS ASIC概要
  • DUS ASIC:封裝分析
  • DUS ASIC:晶片分析
  • 由舊型ASIC的演進
  • 核心處理器功能
  • DUS DSP情結
  • 特殊結構:數位&類比I/O
  • 其他DUS ASIC專用技術分析

第10章 總論

圖表

目錄
Product Code: SDNA-I-2015-001

This report provides a comprehensive technology analysis of the digital baseband unit ASICs within the Ericsson RBS6000 base station platform. The ASICs analyzed are used in the following Ericsson digital units: DUG 10, DUG 20, DUW 10, DUW 20, DUW 30, DUL 20, DUS 31, and DUS 41. There is a total of six Ericsson baseband ASICs contained within this report.

Features

  • Wafer Fabrication ID, Silicon process node ID, Die Size and Package Analysis
  • Die photograph, magnified SEM photographs, X-Ray photographs
  • Die mapping of functional blocks
  • Die mapping of I/Os
  • Die mapping of memory structures
  • Digital unit system architecture
  • DSP core analysis
  • Proprietary technology analysis
  • Total Pages: 157
  • Total Tables: 26
  • Total Exhibits: 163

Table of Contents

EXECUTIVE SUMMARY

  • DU Board Teardowns + ASIC RE Analysis = Invaluable Insight
  • Radio System Architecture History
  • BTS Hardware Development Compared with Software Development
  • Key Takeaways: Carrier Grade Cost Structure Pressure

CHAPTER 1: ERICSSON RADIO SYSTEM ARCHITECTURE

  • 1.1. DU Boards and their ASICs
  • 1.2. Ericsson Radio System Architecture
  • 1.3. SOFTWARE-DEFINED RADIO
  • 1.4. Multi-standard RAN Complexity
  • 1.5. All RAN Ericsson Radio System (ERS)
  • 1.6. DU ASIC CHART Overview

CHAPTER 2: DIGITAL UNIT (DU) OVERVIEW

  • 2.1. DU System-Level Architecture Support for ASICs
  • 2.2. DU Board-Level Architecture
  • 2.3. DUG Subsystem
  • 2.4. DUW Subsystem
  • 2.5. DUL and DUS Subsystem
  • 2.6. Common Operation and Maintenance (O&M) Features
  • 2.7. Board/ASIC Trace and Debug Overview

CHAPTER 3: RBS DIGITAL UNIT (DU) PROCESSING

  • 3.1. DU Analysis Scope/Process
  • 3.2. DUL/DUS Subsystem Functionality
  • 3.3. In-depth ASIC Analysis Process
  • 3.4. Multi-Core Ecosystem
  • 3.5. Atypical Trace and Debug Capabilities
  • 3.6. DU Architectural Summary

CHAPTER 4: DU ASIC OVERVIEW

  • 4.1. ASIC Process Nodes
  • 4.2. ASIC Fabrication Source Analysis
  • 4.3. Silicon Area and Function
  • 4.4. DSP/Multi-Core Evolution

CHAPTER 5: MULTI-CORE/DSP OVERVIEW

  • 5.1. Shift from PowerPC to ARM Ecosystem
  • 5.2. DSP Core Technology/Analysis
  • 5.3. Internal DSP Cores

CHAPTER 6: DUG ASICS FOR GSM

  • 6.1. GSM Processing Overview
  • 6.2. Basic Structure and Architecture
  • 6.3. I/O Analysis
  • 6.4. DUG ASIC-2 Summary of Findings

CHAPTER 7: DUW ASICS FOR W-CDMA

  • 7.1. DUW ASICs Overview
  • 7.2. DUW ASIC #1 Package Analysis
  • 7.3. DUW ASIC #1 Chip Analysis
  • 7.4. DUW ASIC #1 Functional Analysis
  • 7.5. DUW ASIC #2 Package Analysis
  • 7.6. DUW ASIC #2 Chip Analysis
  • 7.7. DUW ASIC #2 Special Structures

CHAPTER 8: DUL ASIC ANALYSIS

  • 8.1. DUL ASIC Overview
  • 8.2. DUL ASIC Package Analysis
  • 8.3. DUL ASIC Chip Analysis
  • 8.4. DUL ASIC CPU Functions
  • 8.5. DSP Functions
  • 8.6. Digital and Analog I/Os

CHAPTER 9: DUS ASIC ANALYSIS

  • 9.1. DUS ASIC Overview
  • 9.2. DUS ASIC Package Analysis
  • 9.3. DUS ASIC Chip Analysis
  • 9.4. Evolution from Previous ASICs
  • 9.5. Core Processor Functions
  • 9.6. DUS DSP Complex
  • 9.7. Special Structures, Digital and Analog I/Os
  • 9.8. Other DUS ASIC Proprietary Technology Analysis

CHAPTER 10: CONCLUSION

APPENDIX A - ACRONYMS

APPENDIX B - CHIP AREAS FOR FUTURE ANALYSIS

TABLES

  • Table 1: Ericsson BTS ASICs and Digital Unit (DU) Hardware
  • Table 2: Six Major Ericsson Digital Baseband Processing ASICs
  • Table 3: Ericsson DUG, DUW, DUL and DUS ASIC Silicon Chart
  • Table 4: Ericsson DUG, DUW, DUL and DUS ASIC Software Chart
  • Table 5: Ericsson DU DSP Block Area Chart; from DUG, DUW, DUL and DUS ASICs
  • Table 6: Essential RT/Embedded Communications Proprietary Technology
  • Table 7: Ericsson BTS ASIC and Digital Unit (DU) Hardware Components
  • Table 8: DUL Chip/ASIC Proprietary Technology Overview
  • Table 9: DUL ASIC Cortex™-R MPCore™ Memory/Register Overview
  • Table 10: DUL ASIC ETM™-R4/R5 Register/Memory Overview
  • Table 11: ETM™-R4/R5 Register/Memory Count
  • Table 12: ARM Cortex™-R5 Dual/MPCore™ Area Analysis
  • Table 13: DUL ASIC DSP Core Overview S
  • Table 14: DUL ASIC Digital and Analog I/Os
  • Table 15: DUS ASIC's Memory Cell Types
  • Table 16: Comparing DUL/DUS ASIC's ARM Cortex™-R MPCore™ Memory Blocks
  • Table 17: Comparing ARM Proprietary Technology in DUL/DUS ASICs
  • Table 18: Comparing I/O and I/O Subsystems in DUL and DUS ASICs
  • Table 19: Comparing ARM Proprietary Technology in DUL/DUS ASICs
  • Table 20: DUS ASIC DSP Area 1 and 2 Memory Blocks
  • Table 21: DUS ASIC DSP H Block Detail
  • Table 22: DUS E Block Ethernet Memory and Buffer Structures
  • Table 23: DUS F Block Memory Structure Analysis
  • Table 24: DUS ASIC G Block Detail
  • Table 25: DUS ASIC “K” Block
  • Table 26: Ericsson Radio System Architectural BTS Roadmap Requirements

EXHIBITS

  • Exhibit 1: Ericsson BTS System Hardware Release, 2003-2016
  • Exhibit 2: RBS 6000 showing “Digital Units” with RUs and RRUs.
  • Exhibit 3: GSM RAN Diagram
  • Exhibit 4: W-CDMA RAN Diagram
  • Exhibit 5: LTE RAN Diagram
  • Exhibit 6: Multi-Radio Access Technology Diagram
  • Exhibit 7: Ericsson Radio System BTS RBS 2000/3000 and RBS 6000 Evolution
  • Exhibit 8: Example of DU Multi-standard Mix Mode RBS System
  • Exhibit 9: Digital Unit Software Architectural Mapping
  • Exhibit 10: Mapping Basic LTE Software Functions to Hardware Proprietary Technology Cores
  • Exhibit 11: Baseband Digital Unit - ERS Baseband DUS XX Block Diagram
  • Exhibit 12: LTE Layer Multi-core SoC Software - Core and DSP
  • Exhibit 13: DUG 20 01 - Front Panel
  • Exhibit 14: DUG 20 01 - Board (Top View) with Heatsinks
  • Exhibit 15: DUW 20 01 - Front Panel
  • Exhibit 16: DUW 10, DUW 20, DUW 30, DUW 11, DUW 31, and DUW 41 versions
  • Exhibit 17: DUW RF/IF board and the Baseband I/O Board
  • Exhibit 18: DUL 20 01 - Front Panel markings, ports, and indicators
  • Exhibit 19: DUS 31 01/DUS 41 01 - Front Panel
  • Exhibit 20: Top View DUL 20 01 Board
  • Exhibit 21: DUS 41 01 Board Bottom View (L) and Top-View (R)
  • Exhibit 22: Direct to DU ASIC Equipment and Managed Objects w/LMT port
  • Exhibit 23: DUL ASIC Identified ROM and Register Structures
  • Exhibit 24: Debug Ports on DUL board with a Serial GigaBit Trace Interface
  • Exhibit 25: DUL Package differences between “R1A” and “R2A” ASIC Revisions
  • Exhibit 26: Ericsson RBS 6000 DU ASICs
  • Exhibit 27: Ericsson DUG, DUW, DUL, and DUS ASICs
  • Exhibit 28: Ericsson DUS ASIC Revisions
  • Exhibit 29: Software/OS Boot Device Loading and Booting ASIC Devices
  • Exhibit 30: DUx Address and ASIC MO Mapping
  • Exhibit 31: Ericsson DUW, DUL, and DUS ASIC Processor/DSP Test Headers
  • Exhibit 32: Shared DUW and DUL ASIC Structures
  • Exhibit 33: ASIC Process Node Identification
  • Exhibit 34: ASIC Process Node Identification
  • Exhibit 35: IBM ASIC Process Technology Roadmap
  • Exhibit 36: TSMC ASIC Process Fabrication Technologies
  • Exhibit 37: Ericsson use of TSMC ASIC Fabrication Technology
  • Exhibit 38: Ericsson DU ASIC Processor Area Comparison
  • Exhibit 39: Ericsson DU ASIC DSP Block Comparisons
  • Exhibit 40: Ericsson DUW ASIC Logic-Based Computation Example
  • Exhibit 41: DUS ASIC RapidIO Buffer
  • Exhibit 42: DSP Proprietary Technology Block Evolution in Ericsson DU ASICs: 2003 to 2011
  • Exhibit 43: SoC & ASIC Design Philosophy at Ericsson
  • Exhibit 44: DSP Core Hardware/Software Tradeoff Example for Ericsson DUW ASIC Design
  • Exhibit 45: Die Size Progression in the Ericsson DUG, DUW, DUL, & DUS ASICs
  • Exhibit 46: DSP PSU (Power-Scaling Unit) Proprietary Technology
  • Exhibit 47: DUG ASICs #1 and #2
  • Exhibit 48: DUG ASIC #1 Markings
  • Exhibit 49: DUG ASIC #1 PowerPC Core
  • Exhibit 50: Digital Unit for GSM-DUG 20 01 Front Panel & Mechanical
  • Exhibit 51: DUG Diagram and Typical Multi-RAT RBS 6000 Use
  • Exhibit 52: DUG Block Diagram
  • Exhibit 53: DUG ASIC #2 Markings
  • Exhibit 54: Digital Unit for GSM-DUG ASIC #2 Overview
  • Exhibit 55: DUG ASIC #2 DSP Core
  • Exhibit 56: DUG ASIC #2 Dual PowerPC Core
  • Exhibit 57: DUG ASIC #2 Processor Core Complex w/PLL
  • Exhibit 58: RBS 6000 DUW Architecture featuring DUW ASICs #1 and #2
  • Exhibit 59: DUW High Level Architecture Block Diagram
  • Exhibit 60: DUW ASIC #1 Package Overview
  • Exhibit 61: DUW ASIC #1 Package X-Ray
  • Exhibit 62: DUW ASIC #1 Top Metal Layer with Magnified Views of the Die Logo and I/O Pads
  • Exhibit 63: DUW ASIC #1 Si Poly Overview
  • Exhibit 64: DUW ASIC #1 Poly Layout SEM
  • Exhibit 65: DUW ASIC #1 Memory Structure Decomposition
  • Exhibit 66: DUW ASIC #1 Memory Structures A-F Block Decomposition
  • Exhibit 67: DUW ASIC #2 Package Overview
  • Exhibit 68: DUW ASIC #2 Package X-Ray
  • Exhibit 69: DUW ASIC #2 Die Overview and Markings
  • Exhibit 70: DUW ASIC #2 Main Feature Overview
  • Exhibit 71: DUW ASIC #2 I/O Match ULMA I/O Subsystems
  • Exhibit 72: DUW ASIC #2 Processing Technology
  • Exhibit 73: DUW ASIC #2 Analog Power Block
  • Exhibit 74: DUW ASIC #2 I/O Structures
  • Exhibit 75: DUW ASIC #2 Special Power Management Structures
  • Exhibit 76: DUW ASIC #2 Special Structure
  • Exhibit 77: DUW ASIC #2 DSP Core Structures vs. DUL ASIC DSP Core Structures
  • Exhibit 78: DUW ASIC #2 Memory Bit-Cell Comparison to DUL ASIC
  • Exhibit 79: DUL ASIC Board-Level Overview
  • Exhibit 80: DUL ASIC Package Revisions
  • Exhibit 81: DUL ASIC Package X-ray with Side-View
  • Exhibit 82: DUL ASIC Package Information
  • Exhibit 83: DUL ASIC Die Size and Top Metal Layer
  • Exhibit 84: DUL ASIC Die Markings
  • Exhibit 85: DUL ASIC Block Overview; DSP Cores, Analog, and I/O Blocks
  • Exhibit 86: DUL ASIC Si Structures
  • Exhibit 87: DUL ASIC Cortex-R MPCore™ Layout Detail
  • Exhibit 88: Suspected ARM CoreSight™-based ETM™
  • Exhibit 89: DUL ASIC Cortex™-R5 Dual/MPCore™ Analysis
  • Exhibit 90: ARM Cortex™-R5 Dual/MPCore™ Area Analysis
  • Exhibit 91: Comparison of ARM Cortex™-R5 Area to Known Cortex™-R4 Chip
  • Exhibit 92: DUL ASIC DSP Core 1
  • Exhibit 93: DUL ASIC DSP Core 2
  • Exhibit 94: DUL/DUS ASIC DSP Control Logic
  • Exhibit 95: DUL ASIC DSP Control Logic and PSU
  • Exhibit 96: DUL ASIC I/O Overview
  • Exhibit 97: Primary DUL ASIC Analog Block AN3 Overview
  • Exhibit 98: Primary DUL ASIC Analog Block AN2 Overview
  • Exhibit 99: DUL ASIC Analog Block AN1 Overview
  • Exhibit 100: Primary DUL Analog Blocks Overview
  • Exhibit 101: DUL ASIC #2 Temperature Sensor Detail
  • Exhibit 102: DUS ASIC Board-Level Overview
  • Exhibit 103: DUS ASIC Package and Die Overview
  • Exhibit 104: DUS ASIC OM, Plan-view, Top, with Die Markings
  • Exhibit 105: DUS ASIC SEM Cross Section (Seal Ring)
  • Exhibit 106: DUS ASIC Memory Types
  • Exhibit 107: DUS ASIC Overview showing ARM Cortex™-R7 MPCore™ and major blocks
  • Exhibit 108: DUL/DUS ASIC DSP Cores Comparison
  • Exhibit 109: DUS ASIC Block Overview; Areas 1 to 5, Analog, and Blocks A-X
  • Exhibit 110: Comparison of DUW and DUL ASICs to the DUL ASIC
  • Exhibit 111: Comparison of ARM Cortex™-R5 Dual Core to ARM Cortex™-R7 MPCore™
  • Exhibit 112: Evolution of DSP Complex in DUL and DUS ASICs
  • Exhibit 113: Cortex™ R-7 MPCore™ ETM™
  • Exhibit 114: DUS ASIC Cortex™ R-7 MPCore™ Block Overview
  • Exhibit 115: DUS ASIC DSP Area 1 and 2 Overview
  • Exhibit 116: ARM/CEVA DSP Complex in DUS ASIC
  • Exhibit 117: DUS ASIC “H” Block - DSP Subsystem
  • Exhibit 118: DUS ASIC Analog/SerDes I/O
  • Exhibit 119: DUS ASIC Analog Structure Overview
  • Exhibit 120: DUS ASIC X-Block Detail and Substructures
  • Exhibit 121: DUS ASIC Digital I/O Blocks Detail, 1-12
  • Exhibit 122: Analog block 1 (AN1) and 3 (AN3) with X-block detail
  • Exhibit 123: DUS ASIC 2- and 4-lane Switch Structures
  • Exhibit 124: DUS ASIC ROM and ARM Core Overview
  • Exhibit 125: DUS ASIC Area 3: ARM Core A3 Block Overview
  • Exhibit 126: DUS ASIC Area 4: ARM Cortex-A* A4 Block Overview
  • Exhibit 127: DUL ASIC I/O Overview
  • Exhibit 128: DUS ASIC Digital I/O Blocks Detail, 1-12
  • Exhibit 129: DUS ASIC B and D Block Switch Structure Overview
  • Exhibit 130: DUS ASIC B Block Switch Structure Detail
  • Exhibit 131: DUS Buffer Memory Block
  • Exhibit 132: DUS ASIC D Block Switch Structure Detail
  • Exhibit 133: DUS ASIC Analog AN2 and its E Block Controller
  • Exhibit 134: DUL ASIC E Block for Ethernet Control and Management
  • Exhibit 135: DUL ASIC F Block Overview
  • Exhibit 136: DUS ASIC G Block - RapidIO Subsystem
  • Exhibit 137: DUS ASIC G Block Structure Overview
  • Exhibit 138: DUS ASIC “G” Block Structure Detail
  • Exhibit 139: DUS ASIC “K” Block Structure Overview
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