全球最新電子零件封裝市場

全球最新電子零件封裝市場 是由出版商BCC Research在2007年05月所出版的。 這份英文市場調查報告書包含173 pages 30 tables 價格從美金4850起跳。

簡介

目錄

Abstract

INTRODUCTION

Miniaturization, portability, speed, and performance efficiency requirements in end-application products have triggered significant advances in chip design methodologies and yields.

Packaging binds the die to the board by acting as physical and electrical interface. Packages not only protect the chip from mechanical damage such as breakage and stress, they also prevent contamination and enable prior testing of the chip before being incorporated into the system. Traditional semiconductor packages have faced two major constraints: size and speed. Hence, it is incumbent that the development in chip design should also be reflected in the packaged being correspondingly efficient.

Despite the critical role played by packaging in the semiconductor manufacturing life cycle, its value is not recognized to the extent required, and the function is generally relegated to the status of being a peripheral function.

The above perception of packaging is set to change with the advent of advanced packaging techniques such as System-in-Package (SiP) that blur the distinction between traditional Electronic Design Automation (EDA) functions and traditional packaging functions. Another phenomenon that reflects the vibrancy in packaging technique is the hectic patenting activity that is breaking new ground in areas of thermal and electrical performance, miniaturization, and process efficiencies. In short, the resurgent drive of the semiconductor industry over the last half decade is being led by advanced packaging techniques. Advanced packaging techniques form the semiconductor industry' s answer to the increasing demand for lower costs, less time to market, portability, and miniaturization. Like most functions in the semiconductor lifecycle, packaging is being increasingly handled by specialists-the Outsourced Semiconductor Packaging and Testing (OSPT) specialists. The report is an effort to derive a snapshot of the OSPT specialist landscape and forecast the future of this category that is truly representative of the semiconductor industry. This report classifies the OSPT revenues across end-user equipment and geographical regions.

The pertinence of this report is highlighted by the variety of design challenges, regulatory requirements, and competition from incumbent technologies that characterize the advanced electronic packaging landscape.

The report shall shed light on the advanced electronic packaging arena in the backdrop of such formidable drivers and equally formidable challenges.

SCOPE OF STUDY

This report:

• Provides a complete technical market analysis of the advanced electronic packaging business - Flipchip, BGA, CSP and others
• Covers assembly, bonding technologies, cooling technologies, materials, modeling and simulation, passive devices, processing, substrates, thermal and mechanical design and many other key areas.
• Provides market forecasts, by major and minor segment, for 2006-2011.
• Covers leading vendors, product innovations and technological breakthroughs.
• Covers end-user markets such as Zigbee, WLAN, computer peripherals, mobile phones, digital cameras, MP3 players, automotive, set-top boxes, power amplifiers, and more.
• Includes standards, stakeholder issues, patent analyses, market shares, R&D breakthroughs, competitive analysis.

INFORMATION SOURCES

This study refers to the following sources:

• Industry consortia
• Company financial details (Form 10-K, annual reports)
• Industry insights in form of published opinions
• Industry sources

ABOUT THE AUTHOR

Kaustubha Parkhi has worked in a broad range of functional roles with leading telecom operators and service providers such as Reliance Infocomm, Ramco Systems and BPL Cellular. He has written on a wide-ranging array of telecommunications and electronics-related subjects based on his critical analysis of the underlying technology and its business impact. Kaustubha holds a B.S degree in Electronics and Telecommunications and a M.B.A. degree in Systems.

Table of Contents

• INTRODUCTION
  • STUDY GOALS AND OBJECTIVES
  • REASONS FOR DOING THE STUDY
  • SCOPE AND FORMAT
  • ABOUT THE AUTHOR
  • INFORMATION SOURCES
  • RELATED BCC REPORTS
  • BCC ONLINE SERVICES
  • DISCLAIMER
• EXECUTIVE SUMMARY
  • Summary Table:
  • GLOBAL MARKET FOR IN-HOUSE AND OUTSOURCED PACKAGING AND TESTING, THROUGH 2011 ($ BILLIONS)
  • Summary Figure:
  • GLOBAL MARKET FOR IN-HOUSE AND OUTSOURCED PACKAGING AND TESTING SALES, 2006 AND 2011 ($ BILLIONS)
• TECHNOLOGY LANDSCAPE
  • TECHNOLOGY LANDSCAPE
    • TECHNOLOGY LANDSCAPE (Continued)
• Figure 1 POSITION OF PACKAGING AND TESTING IN SEMICONDUCTOR MANUFACTURING CYCLE
  • TYPES OF ADVANCED PACKAGING TECHNIQUES
    • TYPES OF ADVANCED PACKAGING ...(CONTINUED)
  • PACKAGE FOOTPRINT REDUCTION: CHIP SCALE PACKAGE (CSP)/WAFER LEVEL PACKAGING (WLP)
    • Introduction
• Table 1 GLOBAL MARKET FORECAST FOR OSPT CSP/WLP SALES, THROUGH 2011 ($ BILLIONS)
  • Background
  • Applications and Case Studies
• Table 2 GLOBAL MARKET FORECAST FOR OSPT CSP, BY SECTOR, THROUGH 2011 ($ BILLIONS)
• Figure 2 GLOBAL MARKET FORECAST FOR OSPT CSP, BY SECTOR, 2004-2011 ($ BILLIONS)
  • Case Study-CSP for High-Brightness LED
• Features and Benefits
  • Size and Weight Efficiency
  • Ease of Implementation
  • Compatibility
  • Mismatch and Revision Elimination
  • Time to Market Reduction
• Implementation Methodologies and Process Enhancements
  • CSP
  • WLP
  • Process Enhancement-Reduction in Particle Defects
  • Process Enhancement-Maxim Integrated Products
• Figure 3 WLP CROSS SECTION
  • Process Enhancement-Tessera
• Figure 4 WLP-COMPLIANT LAYER
  • Process Enhancement-Amkor
• Limitations of CSP/WLP
  • Infrastructure Constraints
  • Cost Concerns
  • Operation Concerns
  • Challenges Associated with Wafer Level Test and Burn-in (WLTBI)
• Global Distribution of OSPT Services Sales by Region
• Table 3 GLOBAL MARKET FORECAST FOR OSPT CSP: DISTRIBUTION BY REGION, THROUGH 2011 ($ BILLIONS)
  • PACKAGE-TO-PCB BONDING-PGA
    • Introduction
    • Features and Benefits
      • Lower Thermal Resistance and High Thermal Heat Dissipation
      • Better Signal Quality
      • High Reliability
• Applications and Case Studies
• Implementation Methodologies and Process Enhancements
  • Implementation Methodology-CPGA
  • Implementation Methodology-PPGA
• PACKAGE-TO-PCB ATTACHMENT/ BONDING: BGA
  • Introduction
• Table 4 GLOBAL MARKET FORECAST FOR OSPT BGA SALES, THROUGH 2011 ($ BILLIONS)
  • Applications and Case Studies
• Table 5 GLOBAL MARKET FORECAST FOR BGA: DISTRIBUTION BY SECTOR, THROUGH 2011 ($ BILLIONS)
• Figure 5 GLOBAL MARKET FORECAST FOR BGA, DISTRIBUTION BY SECTOR, 2004-2011 ($ BILLIONS)
  • Features and Benefits
  • High Density
  • Heat Conduction Efficiency
  • Low Inductance Leads
• Implementation Methodologies and Process Enhancements
  • Implementation Methodologies ...(Continued)
  • Implementation Methodology-PBGA
  • Implementation Methodology-FCBGA
  • Implementation Methodology-CBGA
  • Implementation Methodology-TBGA
  • Implementation Methodology-EBGA
  • Process Enhancement-Ball Placement Equipment
  • Process Enhancement-SolVision
• Limitations and Challenges
  • Unreliability of Solder Balls
  • Complicated, Expensive, and Incomprehensive Inspection Techniques
  • Difficulty in Rectification of Individual Solders
  • Inability to Withstand High Temperature
  • Sensitivity to Moisture
• Global Distribution of OSPT Sales by Region
• Table 6 GLOBAL MARKET FORECAST FOR OSPT BGA, DISTRIBUTION BY REGION, THROUGH 2011 ($ BILLIONS)
  • DIE-TO-PACKAGE SUBSTRATE ATTACHMENT/BONDING: FC
    • Introduction
• Table 7 GLOBAL MARKET FORECAST FOR OSPT FC, THROUGH 2011 ($ BILLIONS)
  • Applications and Case Studies
    • Case Study-Kyocera
    • Case Study-Migration from Wire Bond to FC Packaging
    • Case Study-Amkor
    • Case Study-ASAT
• Table 8 GLOBAL MARKET FORECAST FOR OSPT FC, DISTRIBUTION BY SECTOR, THROUGH 2011 ($ BILLIONS)
• Figure 6 GLOBAL MARKET FORECAST FOR OSPT FC, DISTRIBUTION, BY SECTOR, 2004-2011 ($ BILLIONS)
  • Features and Benefits
    • Size Efficiency
    • Speedy Interconnect
    • I/O Efficiency
    • Cost Benefits
    • Assembly Process Efficiency
  • Implementation Methodologies and Process Enhancements
• Figure 7 OERLIKON MICRON5003 FC BONDER
  • Implementation Methodologies ...(Continued)
  • Implementation Methodologies ...(Continued)
  • Implementation Methodology-Electroless Nickel-Gold FC
  • Process Enhancement-Texas Instruments
  • Process Enhancement-Valtronics
  • Process Enhancement-Henkel
  • Process Enhancement-Stud Bumping
  • Process Enhancement-Precise Flux Deposition Mechanism
• Limitations and Challenges
  • Spacing Constraints
  • Solder Processing Temperature and Material Restrictions
  • Costly Bumping Processes
  • Substrate Concerns
  • Underfill Process Trade-Offs
• Global Distribution of OSPT Services by Region
• Table 9 GLOBAL MARKET FORECAST FOR OSPT FC, DISTRIBUTION BY REGION, THROUGH 2011 ($ BILLIONS)
  • MULTI-FUNCTIONAL INTEGRATION ON THE PACKAGE: MCM
    • Introduction
• Table 10 GLOBAL MARKET FORECAST FOR OSPT MCM, THROUGH 2011 ($ BILLIONS)
  • Applications and Case Studies
    • Case Study-IBM
    • Case Study-MCM in Optical Telecom Applications
    • Case Study-Orsys
• Table 11 GLOBAL MARKET FORECAST FOR OSPT MCM, DISTRIBUTION BY SECTOR, THROUGH 2011 ($ BILLIONS)
• Figure 8 GLOBAL MARKET FORECAST FOR OSPT MCM, DISTRIBUTION BY SECTOR, 2004-2011 ($ BILLIONS)
  • Features and Benefits
    • Better Performance
    • Improved Signal Quality
    • Size Reduction
    • Economic Advantages
  • Implementation Methodologies and Process Enhancements
  • Implementation Methodology-Laminated MCM (MCM-L)
  • Implementation Methodology-Ceramic MCM (MCM-C)
    • Thick Film
    • High Temperature Co-fired Ceramic (HTCC)
    • Low Temperature Co-fired Ceramic (LTCC)
  • Implementation Methodology-Deposited MCM (MCM-D)
    • Classic Thin-Film
    • Silicon Thin-Film
    • Polymer Thin-Film
  • Limitations and Challenges
    • Performance Inefficiencies
    • Architectural Constraints
    • Electrical and Thermal Constraints
    • Cost Constraints
    • Test Constraints
  • Global Distribution of OSPT Sales by Region
• Table 12 GLOBAL MARKET FORECAST FOR OSPT MCM, DISTRIBUTION BY REGION, THROUGH 2011 ($ BILLIONS)
  • MULTI-FUNCTIONAL INTEGRATION ON THE PACKAGE: SIP
    • Introduction
• Table 13 GLOBAL MARKET FORECAST FOR OSPT SIP, THROUGH 2011 ($ BILLIONS)
  • Applications and Case Studies
    • Case Study-Wi2Wi
    • Case Study-NEC
    • Case Study-ChipMOS
    • Case Study-Toshiba
• Figure 9 SIP IN ULTRA-THIN HARD DRIVE
• Figure 10 SIP IN MOBILE PHONE
• Table 14 GLOBAL MARKET FORECAST FOR OSPT SIP, DISTRIBUTION, BY SECTOR, THROUGH 2011 ($ BILLIONS)
• Figure 11 GLOBAL MARKET FORECAST FOR OSPT SIP, DISTRIBUTION BY SECTOR, 2004-2011 ($ BILLIONS)
  • Features and Benefits
    • Size Efficiency
    • Performance Enhancement
    • Design and Review Flexibility
    • Cost Advantage
    • Reduced Time-to-Market
  • Implementation Methodologies and Process Enhancements
• Figure 12 CROSS SECTIONS OF FC AND WIRE-BONDED SIPS
  • Limitations and Challenges
    • Limited Availability of Skills and Resources
    • Re-alignment of EDA Processes
    • Lack of KGD
    • Larger Package Size as Compared to SoC
    • Pressures on Wafering Process
• Table 15 GLOBAL MARKET FORECAST FOR OSPT SIP, DISTRIBUTION BY REGION, THROUGH 2011 ($ BILLIONS)
  • MULTI-FUNCTIONAL INTEGRATION ON THE PACKAGE: POP
    • Introduction
• Table 16 GLOBAL MARKET FORECAST FOR OSPT POP, THROUGH 2011 ($ BILLIONS)
  • Applications and Case Studies
    • Case Study-STATS ChipPAC
    • Case Study-STMicroelectronics
    • Case Study-Toshiba America Electronic Components
• Table 17 GLOBAL MARKET FORECAST FOR OSPT POP, DISTRIBUTION BY SECTOR, THROUGH 2011 ($ BILLIONS)
• Figure 13 GLOBAL MARKET FORECAST FOR OSPT POP, DISTRIBUTION BY SECTOR, 2004-2011 ($ BILLIONS)
  • Features and Benefits
    • Saving in Board Surface Area
    • Ease in System Design
    • Reduction in PCB Complexity
    • Enhanced Performance
    • Reduced Time-to-Market
  • Implementation Methodologies and Process Enhancements
• Figure 14 CROSS SECTION AND TOP VIEW OF PSVFBGA
  • Process Enhancement-IntelLimitations and Challenges
  • Conflict of Interests
  • Over Dependence on Solder Ball Material Characteristics
  • Pressure on PoP(d) Design
• Global Distribution of OSPT Sales by Region
• Table 18 GLOBAL MARKET FORECAST FOR OSPT POP, DISTRIBUTION BY REGION, THROUGH 2011 ($ BILLIONS)
  • INDUSTRY ANALYSIS
• Table 19 GLOBAL MARKET FORECAST FOR SEMICONDUCTOR CHIPS TO ALL INDUSTRY SECTOR END PRODUCTS, THROUGH 2011 ($ BILLIONS)
• Table 20 SHARE OF TOTAL AND OUTSOURCED SEMICONDUCTOR PACKAGING AND SERVICES, THROUGH 2011 (%)
• Figure 15 SHARE OF TOTAL AND OUTSOURCED SEMICONDUCTOR PACKAGING AND SERVICES, 2004-2011 (%)
  • COMPETITION
  • CYCLICALITY
  • FUNDAMENTALS
    • DEMAND FLUCTUATIONS IN THE END PRODUCTS
    • CAPACITY UTILIZATION FLUCTUATIONS
    • PRICING PRESSURES
    • CHANGE IN MIX OF SEMICONDUCTOR PACKAGES
    • SHORT TERM CUSTOMER COMMITMENT DURATIONS
    • RAW MATERIAL AVAILABILITY AND PRICING FLUCTUATIONS
    • IP DISPUTES
    • NATURAL CALAMITIES
    • RISKS ASSOCIATED WITH OPERATIONS IN MULTIPLE NATIONS
  • BUYER/ SUPPLIER INTERPLAY
    • PACKAGING SERVICES
    • TESTING SERVICES
    • OSPT SERVICE PROVIDER-IDM INTERPLAY
  • RAW MATERIALS and value added components FOR ADVANCED PACKAGING
    • DIELECTRICS AND SUBSTRATES
      • Market Overview and Update
  • SOLDERS
    • Market Overview and Update
  • SOCKETS AND INTERCONNECTS
    • Market Overview and Update
  • UNDERFILLS
  • THERMAL MANAGEMENT SOLUTIONS
    • Market Overview and Update
  • WHY OUTSOURCE?
• Table 21 SHARES OF OSPT SERVICES AND IN-HOUSE SEMICONDUCTOR PACKAGING AND TESTING SERVICES MARKETS, THROUGH 2011 (%)
• Figure 16 SHARES OF OSPT SERVICES SALES AND IN-HOUSE SEMICONDUCTOR PACKAGING AND TESTING SERVICES MARKETS, 2004-2011 (%)
  • QUICKER TURNAROUND TIMES
  • FAVORABLE ECONOMIES OF SCALE
  • EMERGENCE OF ATTRACTIVE OUTSOURCING DESTINATIONS
  • FAVORABLE SUPPLY CHAIN
• MARKETS FOR OSPT SERVICES
  • END USER DEVICE APPLICATION MARKET BY SECTOR
• Table 22 GLOBAL SHARE FORECAST OF OSPT SALES, BY SECTOR, THROUGH 2011 (%)
• Figure 17 GLOBAL SHARE FORECAST OF OSPT SALES, BY SECTOR, 2004-2011 (%)
  • Application Market Analysis-Telecommunications
  • Application Market Analysis-Consumer Electronics
  • Application Market Analysis-PC
• Regional Markets
  • Table 23 GLOBAL MARKET SHARE FORECAST FOR OSPT SALES, BY REGION, THROUGH 2011 (%)
• Figure 18 GLOBAL MARKET SHARE FOR OSPT SALES, BY REGION, 2004-2011 (%)
  • Regional Market Analysis-APAC
    • South East Asian Region
    • China
• India
  • Regional Market Analysis-Americas
  • Regional Market Analysis-EMEA
  • DRIVERS
• PORTABILITY AND MINIATURIZATION OF DEVICES
• Table 24 CAGR COMPARISON-OSPT SALES VERSUS OSPT TELECOMMUNICATIONS SALES, THROUGH 2011
• Figure 19 CAGR COMPARISON-OSPT SALES VERSUS OSPT TELECOMMUNICATIONS SALES, 2006-2011 (CAGR%)
• SHRINKING TURNAROUND TIMES
• EMERGENCE OF THE APAC REGION
• Table 25 CAGR COMPARISON-OSPT SALES VERSUS OSPT APAC SALES THROUGH 2011 (CAGR%)
• Table 25 (CONTINUED)
• Figure 20 CAGR COMPARISON-OSPT SALES VERSUS OSPT APAC SALES, 2006-2011 (CAGR%)
• COST-EFFECTIVENESS OF ADVANCED PACKAGING SOLUTIONS
  • ASIC
  • SoC
  • Advantages of SiP and MCM
• Table 26 COMPARISON OF SALES OF ASIC, SOC, MCM AND SIP, THROUGH 2011 ($ BILLIONS)
• Figure 21 COMPARISON OF CAGRS OF ASIC, SOC, MCM AND SIP (CAGR%)
  • STANDARDS BODIES AND ROLE OF INDUSTRY CONSORTIA
    • HIGH DENSITY PACKAGING USER GROUP (HDPUG)
    • INTERNATIONAL ELECTRONICS MANUFACTURING INITIATIVE (INEMI)
    • JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (FORMERLY JOINT ELECTRON DEVICE ENGINEERING COUNCIL)
      • Jedec Solid State ...(Continued)
      • Microelectronics Packaging and Test Engineering Council (MEPTEC)
• REGULATORY CONDITIONS
  • U.S. REGULATIONS
  • ASIAN REGULATIONS
  • WASTE FROM ELECTRICAL AND ELECTRONIC EQUIPMENT (WEEE) DIRECTIVE
  • RESTRICTION ON HAZARDOUS SUBSTANCES (ROHS)
• CHALLENGES
  • IP RELATED DISPUTES
  • IP Related Disputes (Continued)
• CHALLENGES POSED BY REGULATIONS
  • Revamp of the Supply Chain
• Figure 22 TEMPERATURE PROFILE OF EUTECTIC AND PB-FREE SOLDERS
  • Semiconductor Company Strategies
  • Backward Compatibility
  • Wafer Bumping Challenges
• Figure 23 "LEAD FREE" SEAL
  • Tin Whiskers
• CASE STUDY-NATIONAL SEMICONDUCTOR
  • Case Study-National Semiconductor (Continued)
  • Case Study-National Semiconductor (Continued)
• STAKEHOLDER DETAILS
  • CRITERIA FOR STAKEHOLDER CLASSIFICATION
  • CRITICAL REASONS FOR INDIVIDUAL STAKEHOLDER SELECTION
    • CRITICAL REASONS FOR INDIVIDUAL...(CONTINUED)
    • CRITICAL REASONS FOR INDIVIDUAL...(CONTINUED)
    • CRITICAL REASONS FOR INDIVIDUAL...(CONTINUED)
    • CRITICAL REASONS FOR INDIVIDUAL...(CONTINUED)
  • STAKEHOLDER CLASSIFICATION SUMMARY
• Table 27 SUMMARY OF SUPPLIERS AND THEIR PRINCIPAL ACTIVITIES
• Table 27 (CONTINUED)
  • STAKEHOLDER Profiles
• ADVANCED INTERCONNECTIONS
  • Introduction
  • Packaging and Testing Function Value Additions
• ADVANCED SEMICONDUCTOR ENGINEERING (ASE)
  • Introduction
  • Packaging and Testing Function Value Additions
  • Customers
  • Financial Performance
• AMKOR TECHNOLOGIES, INC.
  • Introduction
  • Packaging and Testing Function Value Additions
    • Packaging and ... (Continued)
  • Customers
  • Locations of Operations
  • Financial Performance
• ANSOFT CORP.
  • Introduction
  • Packaging and Testing Function Value Additions
  • Packaging and Testing ... (Continued)
  • Customers
  • Financial Performance
• ASAT HOLDINGS
  • Introduction
  • Packaging and Testing Function Value Additions
  • Customers
  • Locations of Operations
  • Financial Performance
• BRIDGE SEMICONDUCTOR
  • Introduction
  • Packaging and Testing Function Value Additions
• CADENCE DESIGN SYSTEMS
  • Introduction
  • Packaging and Testing Function Value Additions
  • Locations of Operations
  • Financial Performance
• CHARTERED SEMICONDUCTOR MANUFACTURING
  • Introduction
  • Packaging and Testing Function Value Additions
  • Customers
  • Locations of Operations
  • Financial Performance
• CHIPMOS TECHNOLOGIES
  • Introduction
  • Packaging and Testing Function Value Additions
  • Customers
  • Locations of Operations
  • Financial Performance
• FLIPCHIP INTERNATIONAL (FCI)
  • Introduction
  • Packaging and Testing Function Value Additions
    • Packaging and Testing ... (Continued)
  • Customers
  • Locations of Operations
  • Financial Performance
• FUJITSU, LTD.
  • Introduction
  • Packaging and Testing Function Value Additions
  • Locations of Operations
  • Financial Performance
• IBM
  • Introduction
  • Packaging and Testing Function Value Additions
  • Financial Performance
• INTEL
  • Packaging and Testing Function Value Additions
  • Financial Performance
• MICRON TECHNOLOGY, INC.
  • Introduction
  • Packaging and Testing Function Value Additions
  • Financial Performance
• M-SYSTEMS (ACQUIRED BY SANDISK)
  • Introduction
  • Packaging and Testing Function Value Additions
  • Financial Performance
• NATIONAL SEMICONDUCTOR CORP.
  • Introduction
  • Packaging and Testing Function Value Additions
  • Locations of Operations
  • Financial Performance
• NEOCONIX, INC.
  • Introduction
  • Packaging and Testing Function Value Additions
  • Locations of Operations
• PSI Technologies Holdings
  • Introduction
  • Packaging and Testing Function Value Additions
  • Customers
  • Locations of Operations
  • Financial Performance
• SAMSUNG SEMICONDUCTOR, INC.
  • Introduction
  • Packaging and Testing Function Value Additions
  • Locations of Operations
  • Financial Performance
• SILICONWARE PRECISION INDUSTRIES (SPIL)
  • Introduction
  • Packaging and Testing Function Value Additions
  • Packaging And Testing ... (Continued)
  • Locations of Operations
  • Financial Performance
• STMICROELECTRONICS (ST)
  • Introduction
  • Packaging and Testing Function Value Additions
  • Customers
  • Locations of Operations
  • Financial Performance
• STAKTEK
  • Introduction
  • Packaging and Testing Function Value Additions
  • Customers
  • Locations of Operations
  • Financial Performance
• STATS CHIPPAC
  • Introduction
  • Packaging and Testing Function Value Additions
  • Packaging and Testing ... (Continued)
  • Packaging and ...(Continued)
  • Financial Performance
• SYNOPSYS
  • Introduction
  • Packaging and Testing Function Value Additions
  • Customers
  • Financial Performance
• TESSERA TECHNOLOGIES
  • Introduction
  • Packaging and Testing Function Value Additions
  • Packaging and ...(Continued)
  • Figure 24 WLP FOR IMAGE SENSORS
  • Customers
  • Financial Performance
• TOSHIBA AMERICA ELECTRIC COMPONENTS AND SEMICONDUCTORS (TAEC)
  • Introduction
  • Packaging and Testing Function Value Additions
  • Financial Performance
• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY (TSMC)
  • Introduction
  • Packaging and Testing Function Value Additions
  • Locations of Operations
  • Financial Performance
• UNITED MICROELECTRONICS CORP.
  • Introduction
  • Packaging and Testing Function Value Additions
  • Financial Performance
• XRADIA
  • Introduction
  • Packaging and Testing Function Value Additions
  • Financial Performance
• U.S. PATENT ANALYSIS
  • INTRODUCTION
  • GENERAL TRENDS
• Table 28 ADVANCED ELECTRONIC PACKAGING TECHNIQUES: U.S. PATENT TRENDS, 1976-2006
• TRENDS BY COUNTRY
• Figure 25 SHARES OF U.S. PATENTS RELATED TO ADVANCED ELECTRONIC PACKAGING TECHNIQUES, BY COUNTRY, 1976-2006
• Figure 25 (CONTINUED)
  • TRENDS BY ASSIGNEE
• Table 29 ASSIGNEES OF 10 OR MORE U.S. PATENTS RELATED TO ADVANCED ELECTRONIC PACKAGING, 1976-2006
• TRENDS BY CATEGORY
• Table 30 CLASSIFICATION OF U.S. PATENTS RELATED TO ADVANCED ELECTRONIC PACKAGING BY CATEGORY, 1976-2006
• LIST OF TABLES
  • Summary Table:
  • GLOBAL MARKET FOR IN-HOUSE AND OUTSOURCED PACKAGING AND TESTING, THROUGH 2011 ($ BILLIONS)Table 1 GLOBAL MARKET FORECAST FOR OSPT CSP/WLP SALES, THROUGH 2011 ($ BILLIONS)
  • Table 2 GLOBAL MARKET FORECAST FOR OSPT CSP, BY SECTOR, THROUGH 2011 ($ BILLIONS)
  • Table 3 GLOBAL MARKET FORECAST FOR OSPT CSP: DISTRIBUTION BY REGION, THROUGH 2011 ($ BILLIONS)
  • Table 4 GLOBAL MARKET FORECAST FOR OSPT BGA SALES, THROUGH 2011 ($ BILLIONS)
  • Table 5 GLOBAL MARKET FORECAST FOR BGA: DISTRIBUTION BY SECTOR, THROUGH 2011 ($ BILLIONS)
  • Table 6 GLOBAL MARKET FORECAST FOR OSPT BGA, DISTRIBUTION BY REGION, THROUGH 2011 ($ BILLIONS)
  • Table 7 GLOBAL MARKET FORECAST FOR OSPT FC, THROUGH 2011 ($ BILLIONS)
  • Table 8 GLOBAL MARKET FORECAST FOR OSPT FC, DISTRIBUTION BY SECTOR, THROUGH 2011 ($ BILLIONS)
  • Table 9 GLOBAL MARKET FORECAST FOR OSPT FC, DISTRIBUTION BY REGION, THROUGH 2011 ($ BILLIONS)
  • Table 10 GLOBAL MARKET FORECAST FOR OSPT MCM, THROUGH 2011 ($ BILLIONS)
  • Table 11 GLOBAL MARKET FORECAST FOR OSPT MCM, DISTRIBUTION BY SECTOR, THROUGH 2011 ($ BILLIONS)
  • Table 12 GLOBAL MARKET FORECAST FOR OSPT MCM, DISTRIBUTION BY REGION, THROUGH 2011 ($ BILLIONS)
  • Table 13 GLOBAL MARKET FORECAST FOR OSPT SIP, THROUGH 2011 ($ BILLIONS)
  • Table 14 GLOBAL MARKET FORECAST FOR OSPT SIP, DISTRIBUTION, BY SECTOR, THROUGH 2011 ($ BILLIONS)
  • Table 15 GLOBAL MARKET FORECAST FOR OSPT SIP, DISTRIBUTION BY REGION, THROUGH 2011 ($ BILLIONS)
  • Table 16 GLOBAL MARKET FORECAST FOR OSPT POP, THROUGH 2011 ($ BILLIONS)
  • Table 17 GLOBAL MARKET FORECAST FOR OSPT POP, DISTRIBUTION BY SECTOR, THROUGH 2011 ($ BILLIONS)
  • Table 18 GLOBAL MARKET FORECAST FOR OSPT POP, DISTRIBUTION BY REGION, THROUGH 2011 ($ BILLIONS)
  • Table 19 GLOBAL MARKET FORECAST FOR SEMICONDUCTOR CHIPS TO ALL INDUSTRY SECTOR END PRODUCTS, THROUGH 2011 ($ BILLIONS)
  • Table 20 SHARE OF TOTAL AND OUTSOURCED SEMICONDUCTOR PACKAGING AND SERVICES, THROUGH 2011 (%)
  • Table 21 SHARES OF OSPT SERVICES AND IN-HOUSE SEMICONDUCTOR PACKAGING AND TESTING SERVICES MARKETS, THROUGH 2011 (%)
  • Table 22 GLOBAL SHARE FORECAST OF OSPT SALES, BY SECTOR, THROUGH 2011 (%)
  • Table 23 GLOBAL MARKET SHARE FORECAST FOR OSPT SALES, BY REGION, THROUGH 2011 (%)
    • Table 24 CAGR COMPARISON-OSPT SALES VERSUS OSPT TELECOMMUNICATIONS SALES, THROUGH 2011
  • Table 25 CAGR COMPARISON-OSPT SALES VERSUS OSPT APAC SALES THROUGH 2011 (CAGR%)
  • Table 26 COMPARISON OF SALES OF ASIC, SOC, MCM AND SIP, THROUGH 2011 ($ BILLIONS)
  • Table 27 SUMMARY OF SUPPLIERS AND THEIR PRINCIPAL ACTIVITIES
  • Table 28 ADVANCED ELECTRONIC PACKAGING TECHNIQUES: U.S. PATENT TRENDS, 1976-2006
  • Table 29 ASSIGNEES OF 10 OR MORE U.S. PATENTS RELATED TO ADVANCED ELECTRONIC PACKAGING, 1976-2006
  • Table 30 CLASSIFICATION OF U.S. PATENTS RELATED TO ADVANCED ELECTRONIC PACKAGING BY CATEGORY, 1976-2006
• LIST OF FIGURESSummary Figure:
  • GLOBAL MARKET FOR IN-HOUSE AND OUTSOURCED PACKAGING AND TESTING SALES, 2006 AND 2011 ($ BILLIONS)
  • Figure 1 POSITION OF PACKAGING AND TESTING IN SEMICONDUCTOR MANUFACTURING CYCLE
  • Figure 2 GLOBAL MARKET FORECAST FOR OSPT CSP, BY SECTOR, 2004-2011 ($ BILLIONS)
  • Figure 3 WLP CROSS SECTION
  • Figure 4 WLP-COMPLIANT LAYER
  • Figure 5 GLOBAL MARKET FORECAST FOR BGA, DISTRIBUTION BY SECTOR, 2004-2011 ($ BILLIONS)
  • Figure 6 GLOBAL MARKET FORECAST FOR OSPT FC, DISTRIBUTION, BY SECTOR, 2004-2011 ($ BILLIONS)
  • Figure 7 OERLIKON MICRON5003 FC BONDER
  • Figure 8 GLOBAL MARKET FORECAST FOR OSPT MCM, DISTRIBUTION BY SECTOR, 2004-2011 ($ BILLIONS)
  • Figure 9 SIP IN ULTRA-THIN HARD DRIVE
  • Figure 10 SIP IN MOBILE PHONE
  • Figure 11 GLOBAL MARKET FORECAST FOR OSPT SIP, DISTRIBUTION BY SECTOR, 2004-2011 ($ BILLIONS)
  • Figure 12 CROSS SECTIONS OF FC AND WIRE-BONDED SIPS
  • Figure 13 GLOBAL MARKET FORECAST FOR OSPT POP, DISTRIBUTION BY SECTOR, 2004-2011 ($ BILLIONS)
  • Figure 14 CROSS SECTION AND TOP VIEW OF PSVFBGA
  • Figure 15 SHARE OF TOTAL AND OUTSOURCED SEMICONDUCTOR PACKAGING AND SERVICES, 2004-2011 (%)
  • Figure 16 SHARES OF OSPT SERVICES SALES AND IN-HOUSE SEMICONDUCTOR PACKAGING AND TESTING SERVICES MARKETS, 2004-2011 (%)
  • Figure 17 GLOBAL SHARE FORECAST OF OSPT SALES, BY SECTOR, 2004-2011 (%)
  • Figure 18 GLOBAL MARKET SHARE FOR OSPT SALES, BY REGION, 2004-2011 (%)
  • Figure 19 CAGR COMPARISON-OSPT SALES VERSUS OSPT TELECOMMUNICATIONS SALES, 2006-2011 (CAGR%)
  • Figure 20 CAGR COMPARISON-OSPT SALES VERSUS OSPT APAC SALES, 2006-2011 (CAGR%)
  • Figure 21 COMPARISON OF CAGRS OF ASIC, SOC, MCM AND SIP (CAGR%)
  • Figure 22 TEMPERATURE PROFILE OF EUTECTIC AND PB-FREE SOLDERS
  • Figure 23 "LEAD FREE" SEAL
  • Figure 24 WLP FOR IMAGE SENSORS
  • Figure 25 SHARES OF U.S. PATENTS RELATED TO ADVANCED ELECTRONIC PACKAGING TECHNIQUES, BY COUNTRY, 1976-2006

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