Abstract
In mid-1997, semiconductor suppliers and the companies that produce chip-manufacturing equipment were set to implement building ICs on 300mm (12-in.) wafers. A massive R&D effort, estimated at slightly more than $4 billion expended so far, has been under way for three or more years to develop the technologies and equipment for the big wafers.
Copper and low-K helped push back the 300mm front. The new interconnect technologies don' t just increase chip performance; they also help make higher chip density possible. The more you improve density, the more ICs you make per wafer, and the less you need a bigger wafer.
The move to copper is going to take longer because the industry expended so much of its reserves on 300mm. Badly burned industry players are going to be twice as cautious moving forward.
Overcapacity in the semiconductor industry moved 300mm processing back to the forefront in 2000.
In a shift away from the recent trend toward outsourced semiconductor production, Integrated Device Manufacturers (IDMs) appear to be returning to their initial approach to chip making: using internal manufacturing to achieve economies of scale.
This trend is manifesting itself in the number of 300mm fabs that will be operated by IDMs vs. those owned by foundries. In 2002, 14 300mm facilities were in production. An estimated 21 percent of those fabs were owned by pure-play foundries. In 2004, the number of 300mm fabs reached 24, with 29 percent of them being owned by foundries.
However, by 2006 there were 47 300mm fabs in production, but only 19 percent will be owned by pure-play foundries. Over the next two years, only one new 300mm fab owned by a pure-play foundry will be built. With their 300mm capacity additions, IDMs will transition production from external foundries to internal fabs.
The pure-play foundries will continue to serve the expanding fabless semiconductor companies and serve as capacity buffers for the major IDMs. However, the key question facing the pure-play foundry service providers is how much demand will shift out of the foundries once internal 300mm capacity becomes available at the IDMs.
New construction will be 300mm related, as DRAM fabs and foundries continue to move to the larger wafers. But future planned 300mm fabs also show a significant increase in the number of fabs devoted to logic and flash memory products, with a corresponding reduction in the dominance of DRAM and foundry applications.
All of this expansion most likely will leave the semiconductor industry vulnerable to a new round of overcapacity and severe price declines.
The benefits of copper are well known, but the problems encountered by chip manufacturers were underestimated when then began evaluating the technology. In facts, initial enthusiasm turned to euphoria for the copper tool manufacturers.
The most significant problems encountered with the copper dual damascene process center around copper deposition and copper CMP, and equipment suppliers are working to enhance the quality of their equipment, processes, and materials.
CMP of copper is more complex than other metals because of the need to remove the tantalum or tantalum nitride barrier layers and copper uniformly without overpolishing any features. Copper' s physical properties add to the polish difficulties. Unlike tungsten, it is a soft metal and subject to scratching and embedded particles during polishing. If one uses a traditional one-step process to planarize copper, dishing (overpolishing) of the copper results as the pad reaches the much harder Ta or TaN barrier.
This report discusses the technological and economic impact on the 300mm/Cu/Low-K convergence. This report discusses the timing, trends, issues, and market analysis of 300mm wafers/tools, copper deposition/etch/CMP, and low-k materials. Markets are analyzed and projected.
Table of Contents
Chapter 1 Introduction
Chapter 2 Executive Summary
- 2.1 Summary of Technical Issues
- 2.2 Summary of Market Forecasts
Chapter 3 300mm Wafer Issues and Trends
- 3.1 Introduction
- 3.2 Industry Consortia
- 3.2.1 International Sematech
- 3.2.2 SEMI
- 3.2.3 SELETE
- 3.2.4 J300
- 3.2.5 SEA
- 3.2.6 MEDEA
- 3.3 Benefits of 300mm Wafers
- 3.4 Impact on Small IC Manufacturers
- 3.5 Impact on ASIC Manufacturers
- 3.6 Costs
- 3.6.1 Cost Breakdown
- 3.6.2 Requirements For IC Manufacturers
- 3.7 Impact on Automation
- 3.7.1 Software
- 3.7.2 Minienvironments
- 3.7.3 Robots
- 3.7.4 Cluster Tools
- 3.8 300 mm Fab Construction Plans
- 3.9 300mm Prime
- 3.10 450mm Fabs
- 3.10.1
- 3.10.2 450mm Wafer Technical Issues
- 3.10.3 Economic Challenges
Chapter 4 Copper Issues and Trends
- 4.1 Advantages of Copper
- 4.2 Copper Processing Challenges
- 4.3 Metal Deposition
- 4.3.1 Seed Layer
- 4.3.2 Bulk Copper Fill
- 4.4 Barriers
- 4.5 Planarization
- 4.6 Metrology
- 4.7 Competing against Aluminum Damascene
- 4.8 Equipment Suppliers' Copper Electroplating Products
- 4.9 IC Manufacturers' Copper Plans
- 4.10 Summary
- 4.10.1 Advantages/Disadvantages of Cu
- 4.10.2 Processing Issues
- 4.10.3 Challenges
Chapter 5 Low-K Dielectric Issues and Trends
- 5.1 Introduction
- 5.2 Ideal Dielectric
- 5.3 Types of Low-K Dielectrics
- 5.3.1 FSG
- 5.3.2 HSQ
- 5.3.3 Nanoporous Silica
- 5.3.4 Spin-on Polymers
- 5.3.5 BCB
- 5.3.6 Flowfill
- 5.3.7 CVD
- 5.3.8 AF4
- 5.3.9 PTFE
- 5.4 Processing Issues
- 5.5 Summary
- 5.5.1 Integration Issues
- 5.5.2 Low-K Dielectric Issues
Chapter 6 Market Analysis
- 6.1 Semiconductor Market
- 6.2 Road to Recovery
- 6.3 Market Forecast Assumptions
- 6.4 300mm Wafer Market
- 6.5 300mm Equipment Market
- 6.5.1 300mm Equipment Tools
- 6.5.2 Factory Automation in 300mm Fab Market
- 6.6 Copper Processing Equipment Market
- 6.7 Low-K Market
TABLES
- 1.1 Planned 300mm Fab Construction
- 3.1 Increase in Wafer Sizes
- 3.2 Cost of 300mm Fab
- 3.3 300mm Fab Construction Plans
- 3.4 Generic Model For CZ Crystal Yield
- 5.1 Low-K Material Requirements
- 5.2 Low-K Materials
- 6.1 Worldwide Market Forecast of Si Wafers
- 6.2 Worldwide Market Forecast of 300mm Equipment
- 6.3 Process Tool Automation For 300mm Fabs
- 6.4 Worldwide Forecast of Automation Transfer Tools
- 6.5 Interconnect Technology Requirements
- 6.6 Worldwide Forecast of Copper Processing Equipment
- 6.7 Worldwide Forecast of Low-K Market
FIGURES
- 3.1 Selete' s Program Results
- 3.2 Larger Die Sizes More Efficiently Utilize 300mm Wafer Area
- 3.3 Increase in IC Size With Time
- 3.4 Economy Of Scale Factor
- 3.5 300mm and 200mm Fab Cost Comparison
- 3.6 300mm Fab Equipment Installs 2007
- 3.7 300mm Fab Equipment Installs 2006
- 3.8 300mm Fabs By Year 2000-2008
- 3.9 300mm Fabs By Location By Type - 2000-2008
- 3.10 Wafer Shipments Forecast
- 3.11 Wafer Shipments 1973-2005
- 3.12 Wafer Thickness Trends With Diameter
- 3.13 Polysilicon Usage By The Solar Industry
- 3.14 Increasing Cost Of Wafer With Time
- 4.1 Reduced Complexity of Copper Interconnect
- 4.2 Interconnect Delay for Copper
- 4.3 ALD Versus PVD Copper Barrier
- 4.4 Copper CMP Steps And Challenges
- 4.5 Electromigration Resistance
- 4.6 Metal Diffusion Barrier
- 4.7 Cu Planarization Process
- 4.8 Copper ECMD Process
- 4.9 Damascus Complete Copper
- 4.10 Copper/Low-K Interconnect Schemes
- 4.11 Copper And Low-K Integration Concerns
- 5.1 Low-K Roadmap
- 6.1 300mm Wafer Market As Percentage of Total Market
- 6.2 Electrochemical Deposition Market Shares - Revenues
- 6.3 Copper Implementation By Geographic Region
- 6.4 Copper Implementation By Feature Size
- 6.5 Low-K Deposition Market Shares
